220 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;  in intel_emit_post_sync_nonzero_flush()
257 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;  in gen6_render_ring_flush()
330 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;  in gen7_render_ring_flush()
415 	u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;  in gen8_render_ring_flush()
697 	ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);  in intel_init_pipe_control()
705 			 ring->name, ring->scratch.gtt_offset);  in intel_init_pipe_control()
1245 		u64 gtt_offset = signaller->semaphore.signal_ggtt[i];  in gen8_rcs_signal()  local
1246 		if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)  in gen8_rcs_signal()
1254 		intel_ring_emit(signaller, lower_32_bits(gtt_offset));  in gen8_rcs_signal()
1255 		intel_ring_emit(signaller, upper_32_bits(gtt_offset));  in gen8_rcs_signal()
1286 		u64 gtt_offset = signaller->semaphore.signal_ggtt[i];  in gen8_xcs_signal()  local
1287 		if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)  in gen8_xcs_signal()
1293 		intel_ring_emit(signaller, lower_32_bits(gtt_offset) |  in gen8_xcs_signal()
1295 		intel_ring_emit(signaller, upper_32_bits(gtt_offset));  in gen8_xcs_signal()
1466 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;  in pc_render_add_request()
1484 	intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);  in pc_render_add_request()
1503 	intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);  in pc_render_add_request()
1848 	u32 cs_offset = ring->scratch.gtt_offset;  in i830_dispatch_execbuffer()
2778 		ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);  in intel_init_render_ring_buffer()