2480 			       u32 invalidate, u32 flush)  in gen6_bsd_ring_flush()  argument
2600 			   u32 invalidate, u32 flush)  in gen6_ring_flush()  argument
2675 		ring->flush = gen8_render_ring_flush;  in intel_init_render_ring_buffer()
2690 		ring->flush = gen7_render_ring_flush;  in intel_init_render_ring_buffer()
2692 			ring->flush = gen6_render_ring_flush;  in intel_init_render_ring_buffer()
2721 		ring->flush = gen4_render_ring_flush;  in intel_init_render_ring_buffer()
2731 			ring->flush = gen2_render_ring_flush;  in intel_init_render_ring_buffer()
2733 			ring->flush = gen4_render_ring_flush;  in intel_init_render_ring_buffer()
2808 		ring->flush = gen6_bsd_ring_flush;  in intel_init_bsd_ring_buffer()
2847 		ring->flush = bsd_ring_flush;  in intel_init_bsd_ring_buffer()
2880 	ring->flush = gen6_bsd_ring_flush;  in intel_init_bsd2_ring_buffer()
2910 	ring->flush = gen6_ring_flush;  in intel_init_blt_ring_buffer()
2967 	ring->flush = gen6_ring_flush;  in intel_init_vebox_ring_buffer()
3017 	ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);  in intel_ring_flush_all_caches()
3038 	ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);  in intel_ring_invalidate_all_caches()