179 	if (dev_priv->psr.aux_frame_sync)  in hsw_psr_enable_sink()
264 	uint32_t idle_frames = dev_priv->vbt.psr.idle_frames ?  in hsw_psr_enable_source()
265 			       dev_priv->vbt.psr.idle_frames + 1 : 5;  in hsw_psr_enable_source()
285 	if (dev_priv->psr.psr2_support)  in hsw_psr_enable_source()
298 	lockdep_assert_held(&dev_priv->psr.lock);  in intel_psr_match_conditions()
302 	dev_priv->psr.source_ok = false;  in intel_psr_match_conditions()
327 	if (!IS_VALLEYVIEW(dev) && ((dev_priv->vbt.psr.full_link) ||  in intel_psr_match_conditions()
333 	dev_priv->psr.source_ok = true;  in intel_psr_match_conditions()
344 	WARN_ON(dev_priv->psr.active);  in intel_psr_activate()
345 	lockdep_assert_held(&dev_priv->psr.lock);  in intel_psr_activate()
357 	dev_priv->psr.active = true;  in intel_psr_activate()
383 	mutex_lock(&dev_priv->psr.lock);  in intel_psr_enable()
384 	if (dev_priv->psr.enabled) {  in intel_psr_enable()
392 	dev_priv->psr.busy_frontbuffer_bits = 0;  in intel_psr_enable()
397 		if (dev_priv->psr.psr2_support) {  in intel_psr_enable()
401 				dev_priv->psr.psr2_support = false;  in intel_psr_enable()
430 	dev_priv->psr.enabled = intel_dp;  in intel_psr_enable()
432 	mutex_unlock(&dev_priv->psr.lock);  in intel_psr_enable()
444 	if (dev_priv->psr.active) {  in vlv_psr_disable()
456 		dev_priv->psr.active = false;  in vlv_psr_disable()
468 	if (dev_priv->psr.active) {  in hsw_psr_disable()
477 		dev_priv->psr.active = false;  in hsw_psr_disable()
495 	mutex_lock(&dev_priv->psr.lock);  in intel_psr_disable()
496 	if (!dev_priv->psr.enabled) {  in intel_psr_disable()
497 		mutex_unlock(&dev_priv->psr.lock);  in intel_psr_disable()
506 	dev_priv->psr.enabled = NULL;  in intel_psr_disable()
507 	mutex_unlock(&dev_priv->psr.lock);  in intel_psr_disable()
509 	cancel_delayed_work_sync(&dev_priv->psr.work);  in intel_psr_disable()
515 		container_of(work, typeof(*dev_priv), psr.work.work);  in intel_psr_work()
516 	struct intel_dp *intel_dp = dev_priv->psr.enabled;  in intel_psr_work()
538 	mutex_lock(&dev_priv->psr.lock);  in intel_psr_work()
539 	intel_dp = dev_priv->psr.enabled;  in intel_psr_work()
549 	if (dev_priv->psr.busy_frontbuffer_bits)  in intel_psr_work()
554 	mutex_unlock(&dev_priv->psr.lock);  in intel_psr_work()
560 	struct intel_dp *intel_dp = dev_priv->psr.enabled;  in intel_psr_exit()
565 	if (!dev_priv->psr.active)  in intel_psr_exit()
598 	dev_priv->psr.active = false;  in intel_psr_exit()
626 	mutex_lock(&dev_priv->psr.lock);  in intel_psr_single_frame_update()
627 	if (!dev_priv->psr.enabled) {  in intel_psr_single_frame_update()
628 		mutex_unlock(&dev_priv->psr.lock);  in intel_psr_single_frame_update()
632 	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;  in intel_psr_single_frame_update()
644 	mutex_unlock(&dev_priv->psr.lock);  in intel_psr_single_frame_update()
666 	mutex_lock(&dev_priv->psr.lock);  in intel_psr_invalidate()
667 	if (!dev_priv->psr.enabled) {  in intel_psr_invalidate()
668 		mutex_unlock(&dev_priv->psr.lock);  in intel_psr_invalidate()
672 	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;  in intel_psr_invalidate()
676 	dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;  in intel_psr_invalidate()
681 	mutex_unlock(&dev_priv->psr.lock);  in intel_psr_invalidate()
705 	mutex_lock(&dev_priv->psr.lock);  in intel_psr_flush()
706 	if (!dev_priv->psr.enabled) {  in intel_psr_flush()
707 		mutex_unlock(&dev_priv->psr.lock);  in intel_psr_flush()
711 	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;  in intel_psr_flush()
715 	dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;  in intel_psr_flush()
737 	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)  in intel_psr_flush()
738 		schedule_delayed_work(&dev_priv->psr.work,  in intel_psr_flush()
740 	mutex_unlock(&dev_priv->psr.lock);  in intel_psr_flush()
754 	INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);  in intel_psr_init()
755 	mutex_init(&dev_priv->psr.lock);  in intel_psr_init()