193 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \  argument
195 	reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
196 	reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
199 #define ASSIGN_CTX_PML4(ppgtt, reg_state) { \  argument
200 	reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
201 	reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
364 	uint32_t *reg_state;  in execlists_update_context()  local
371 	reg_state = kmap_atomic(page);  in execlists_update_context()
373 	reg_state[CTX_RING_TAIL+1] = rq->tail;  in execlists_update_context()
374 	reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj);  in execlists_update_context()
382 		ASSIGN_CTX_PDP(ppgtt, reg_state, 3);  in execlists_update_context()
383 		ASSIGN_CTX_PDP(ppgtt, reg_state, 2);  in execlists_update_context()
384 		ASSIGN_CTX_PDP(ppgtt, reg_state, 1);  in execlists_update_context()
385 		ASSIGN_CTX_PDP(ppgtt, reg_state, 0);  in execlists_update_context()
388 	kunmap_atomic(reg_state);  in execlists_update_context()
2237 	uint32_t *reg_state;  in populate_lr_context()  local
2260 	reg_state = kmap_atomic(page);  in populate_lr_context()
2268 		reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);  in populate_lr_context()
2270 		reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);  in populate_lr_context()
2271 	reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;  in populate_lr_context()
2272 	reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);  in populate_lr_context()
2273 	reg_state[CTX_CONTEXT_CONTROL+1] =  in populate_lr_context()
2277 	reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);  in populate_lr_context()
2278 	reg_state[CTX_RING_HEAD+1] = 0;  in populate_lr_context()
2279 	reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);  in populate_lr_context()
2280 	reg_state[CTX_RING_TAIL+1] = 0;  in populate_lr_context()
2281 	reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);  in populate_lr_context()
2285 	reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);  in populate_lr_context()
2286 	reg_state[CTX_RING_BUFFER_CONTROL+1] =  in populate_lr_context()
2288 	reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;  in populate_lr_context()
2289 	reg_state[CTX_BB_HEAD_U+1] = 0;  in populate_lr_context()
2290 	reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;  in populate_lr_context()
2291 	reg_state[CTX_BB_HEAD_L+1] = 0;  in populate_lr_context()
2292 	reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;  in populate_lr_context()
2293 	reg_state[CTX_BB_STATE+1] = (1<<5);  in populate_lr_context()
2294 	reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;  in populate_lr_context()
2295 	reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;  in populate_lr_context()
2296 	reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;  in populate_lr_context()
2297 	reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;  in populate_lr_context()
2298 	reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;  in populate_lr_context()
2299 	reg_state[CTX_SECOND_BB_STATE+1] = 0;  in populate_lr_context()
2301 		reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;  in populate_lr_context()
2302 		reg_state[CTX_BB_PER_CTX_PTR+1] = 0;  in populate_lr_context()
2303 		reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;  in populate_lr_context()
2304 		reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;  in populate_lr_context()
2305 		reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;  in populate_lr_context()
2306 		reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;  in populate_lr_context()
2311 			reg_state[CTX_RCS_INDIRECT_CTX+1] =  in populate_lr_context()
2315 			reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =  in populate_lr_context()
2318 			reg_state[CTX_BB_PER_CTX_PTR+1] =  in populate_lr_context()
2323 	reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);  in populate_lr_context()
2324 	reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;  in populate_lr_context()
2325 	reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;  in populate_lr_context()
2326 	reg_state[CTX_CTX_TIMESTAMP+1] = 0;  in populate_lr_context()
2327 	reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);  in populate_lr_context()
2328 	reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);  in populate_lr_context()
2329 	reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);  in populate_lr_context()
2330 	reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);  in populate_lr_context()
2331 	reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);  in populate_lr_context()
2332 	reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);  in populate_lr_context()
2333 	reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);  in populate_lr_context()
2334 	reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);  in populate_lr_context()
2341 		ASSIGN_CTX_PML4(ppgtt, reg_state);  in populate_lr_context()
2348 		ASSIGN_CTX_PDP(ppgtt, reg_state, 3);  in populate_lr_context()
2349 		ASSIGN_CTX_PDP(ppgtt, reg_state, 2);  in populate_lr_context()
2350 		ASSIGN_CTX_PDP(ppgtt, reg_state, 1);  in populate_lr_context()
2351 		ASSIGN_CTX_PDP(ppgtt, reg_state, 0);  in populate_lr_context()
2355 		reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);  in populate_lr_context()
2356 		reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE;  in populate_lr_context()
2357 		reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev);  in populate_lr_context()
2360 	kunmap_atomic(reg_state);  in populate_lr_context()
2537 		uint32_t *reg_state;  in intel_lr_context_reset()  local
2548 		reg_state = kmap_atomic(page);  in intel_lr_context_reset()
2550 		reg_state[CTX_RING_HEAD+1] = 0;  in intel_lr_context_reset()
2551 		reg_state[CTX_RING_TAIL+1] = 0;  in intel_lr_context_reset()
2553 		kunmap_atomic(reg_state);  in intel_lr_context_reset()