193 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \  argument
194 	const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n));	\
199 #define ASSIGN_CTX_PML4(ppgtt, reg_state) { \  argument
200 	reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
201 	reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
360 	struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;  in execlists_update_context()  local
376 	if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {  in execlists_update_context()
382 		ASSIGN_CTX_PDP(ppgtt, reg_state, 3);  in execlists_update_context()
383 		ASSIGN_CTX_PDP(ppgtt, reg_state, 2);  in execlists_update_context()
384 		ASSIGN_CTX_PDP(ppgtt, reg_state, 1);  in execlists_update_context()
385 		ASSIGN_CTX_PDP(ppgtt, reg_state, 0);  in execlists_update_context()
1551 	struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;  in intel_logical_ring_emit_pdps()  local
1563 		const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);  in intel_logical_ring_emit_pdps()
1581 	bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);  in gen8_emit_bb_start()  local
1590 	if (req->ctx->ppgtt &&  in gen8_emit_bb_start()
1591 	    (intel_ring_flag(req->ring) & req->ctx->ppgtt->pd_dirty_rings)) {  in gen8_emit_bb_start()
1599 		req->ctx->ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->ring);  in gen8_emit_bb_start()
1608 				(ppgtt<<8) |  in gen8_emit_bb_start()
2235 	struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;  in populate_lr_context()  local
2240 	if (!ppgtt)  in populate_lr_context()
2241 		ppgtt = dev_priv->mm.aliasing_ppgtt;  in populate_lr_context()
2336 	if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {  in populate_lr_context()
2341 		ASSIGN_CTX_PML4(ppgtt, reg_state);  in populate_lr_context()
2348 		ASSIGN_CTX_PDP(ppgtt, reg_state, 3);  in populate_lr_context()
2349 		ASSIGN_CTX_PDP(ppgtt, reg_state, 2);  in populate_lr_context()
2350 		ASSIGN_CTX_PDP(ppgtt, reg_state, 1);  in populate_lr_context()
2351 		ASSIGN_CTX_PDP(ppgtt, reg_state, 0);  in populate_lr_context()