1114 #define wa_ctx_emit(batch, index, cmd)					\  argument
1120 		batch[__index] = (cmd);					\
1141 						uint32_t *const batch,  in gen8_emit_flush_coherentl3_wa()  argument
1155 	wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |  in gen8_emit_flush_coherentl3_wa()
1157 	wa_ctx_emit(batch, index, GEN8_L3SQCREG4);  in gen8_emit_flush_coherentl3_wa()
1158 	wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);  in gen8_emit_flush_coherentl3_wa()
1159 	wa_ctx_emit(batch, index, 0);  in gen8_emit_flush_coherentl3_wa()
1161 	wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));  in gen8_emit_flush_coherentl3_wa()
1162 	wa_ctx_emit(batch, index, GEN8_L3SQCREG4);  in gen8_emit_flush_coherentl3_wa()
1163 	wa_ctx_emit(batch, index, l3sqc4_flush);  in gen8_emit_flush_coherentl3_wa()
1165 	wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));  in gen8_emit_flush_coherentl3_wa()
1166 	wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |  in gen8_emit_flush_coherentl3_wa()
1168 	wa_ctx_emit(batch, index, 0);  in gen8_emit_flush_coherentl3_wa()
1169 	wa_ctx_emit(batch, index, 0);  in gen8_emit_flush_coherentl3_wa()
1170 	wa_ctx_emit(batch, index, 0);  in gen8_emit_flush_coherentl3_wa()
1171 	wa_ctx_emit(batch, index, 0);  in gen8_emit_flush_coherentl3_wa()
1173 	wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |  in gen8_emit_flush_coherentl3_wa()
1175 	wa_ctx_emit(batch, index, GEN8_L3SQCREG4);  in gen8_emit_flush_coherentl3_wa()
1176 	wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);  in gen8_emit_flush_coherentl3_wa()
1177 	wa_ctx_emit(batch, index, 0);  in gen8_emit_flush_coherentl3_wa()
1231 				    uint32_t *const batch,  in gen8_init_indirectctx_bb()  argument
1238 	wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);  in gen8_init_indirectctx_bb()
1242 		int rc = gen8_emit_flush_coherentl3_wa(ring, batch, index);  in gen8_init_indirectctx_bb()
1252 	wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));  in gen8_init_indirectctx_bb()
1253 	wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |  in gen8_init_indirectctx_bb()
1257 	wa_ctx_emit(batch, index, scratch_addr);  in gen8_init_indirectctx_bb()
1258 	wa_ctx_emit(batch, index, 0);  in gen8_init_indirectctx_bb()
1259 	wa_ctx_emit(batch, index, 0);  in gen8_init_indirectctx_bb()
1260 	wa_ctx_emit(batch, index, 0);  in gen8_init_indirectctx_bb()
1264 		wa_ctx_emit(batch, index, MI_NOOP);  in gen8_init_indirectctx_bb()
1294 			       uint32_t *const batch,  in gen8_init_perctx_bb()  argument
1300 	wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);  in gen8_init_perctx_bb()
1302 	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);  in gen8_init_perctx_bb()
1309 				    uint32_t *const batch,  in gen9_init_indirectctx_bb()  argument
1319 		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);  in gen9_init_indirectctx_bb()
1322 	ret = gen8_emit_flush_coherentl3_wa(ring, batch, index);  in gen9_init_indirectctx_bb()
1329 		wa_ctx_emit(batch, index, MI_NOOP);  in gen9_init_indirectctx_bb()
1336 			       uint32_t *const batch,  in gen9_init_perctx_bb()  argument
1345 		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));  in gen9_init_perctx_bb()
1346 		wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);  in gen9_init_perctx_bb()
1347 		wa_ctx_emit(batch, index,  in gen9_init_perctx_bb()
1349 		wa_ctx_emit(batch, index, MI_NOOP);  in gen9_init_perctx_bb()
1355 		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);  in gen9_init_perctx_bb()
1357 	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);  in gen9_init_perctx_bb()
1395 	uint32_t *batch;  in intel_init_workaround_bb()  local
1422 	batch = kmap_atomic(page);  in intel_init_workaround_bb()
1428 					       batch,  in intel_init_workaround_bb()
1435 					  batch,  in intel_init_workaround_bb()
1442 					       batch,  in intel_init_workaround_bb()
1449 					  batch,  in intel_init_workaround_bb()
1456 	kunmap_atomic(batch);  in intel_init_workaround_bb()