Lines Matching refs:val
141 u32 val = I915_READ(VIDEO_DIP_CTL); in g4x_write_infoframe() local
144 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); in g4x_write_infoframe()
146 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ in g4x_write_infoframe()
147 val |= g4x_infoframe_index(type); in g4x_write_infoframe()
149 val &= ~g4x_infoframe_enable(type); in g4x_write_infoframe()
151 I915_WRITE(VIDEO_DIP_CTL, val); in g4x_write_infoframe()
163 val |= g4x_infoframe_enable(type); in g4x_write_infoframe()
164 val &= ~VIDEO_DIP_FREQ_MASK; in g4x_write_infoframe()
165 val |= VIDEO_DIP_FREQ_VSYNC; in g4x_write_infoframe()
167 I915_WRITE(VIDEO_DIP_CTL, val); in g4x_write_infoframe()
176 u32 val = I915_READ(VIDEO_DIP_CTL); in g4x_infoframe_enabled() local
178 if ((val & VIDEO_DIP_ENABLE) == 0) in g4x_infoframe_enabled()
181 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) in g4x_infoframe_enabled()
184 return val & (VIDEO_DIP_ENABLE_AVI | in g4x_infoframe_enabled()
197 u32 val = I915_READ(reg); in ibx_write_infoframe() local
199 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); in ibx_write_infoframe()
201 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ in ibx_write_infoframe()
202 val |= g4x_infoframe_index(type); in ibx_write_infoframe()
204 val &= ~g4x_infoframe_enable(type); in ibx_write_infoframe()
206 I915_WRITE(reg, val); in ibx_write_infoframe()
218 val |= g4x_infoframe_enable(type); in ibx_write_infoframe()
219 val &= ~VIDEO_DIP_FREQ_MASK; in ibx_write_infoframe()
220 val |= VIDEO_DIP_FREQ_VSYNC; in ibx_write_infoframe()
222 I915_WRITE(reg, val); in ibx_write_infoframe()
233 u32 val = I915_READ(reg); in ibx_infoframe_enabled() local
235 if ((val & VIDEO_DIP_ENABLE) == 0) in ibx_infoframe_enabled()
238 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) in ibx_infoframe_enabled()
241 return val & (VIDEO_DIP_ENABLE_AVI | in ibx_infoframe_enabled()
255 u32 val = I915_READ(reg); in cpt_write_infoframe() local
257 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); in cpt_write_infoframe()
259 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ in cpt_write_infoframe()
260 val |= g4x_infoframe_index(type); in cpt_write_infoframe()
265 val &= ~g4x_infoframe_enable(type); in cpt_write_infoframe()
267 I915_WRITE(reg, val); in cpt_write_infoframe()
279 val |= g4x_infoframe_enable(type); in cpt_write_infoframe()
280 val &= ~VIDEO_DIP_FREQ_MASK; in cpt_write_infoframe()
281 val |= VIDEO_DIP_FREQ_VSYNC; in cpt_write_infoframe()
283 I915_WRITE(reg, val); in cpt_write_infoframe()
293 u32 val = I915_READ(reg); in cpt_infoframe_enabled() local
295 if ((val & VIDEO_DIP_ENABLE) == 0) in cpt_infoframe_enabled()
298 return val & (VIDEO_DIP_ENABLE_AVI | in cpt_infoframe_enabled()
312 u32 val = I915_READ(reg); in vlv_write_infoframe() local
314 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); in vlv_write_infoframe()
316 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ in vlv_write_infoframe()
317 val |= g4x_infoframe_index(type); in vlv_write_infoframe()
319 val &= ~g4x_infoframe_enable(type); in vlv_write_infoframe()
321 I915_WRITE(reg, val); in vlv_write_infoframe()
333 val |= g4x_infoframe_enable(type); in vlv_write_infoframe()
334 val &= ~VIDEO_DIP_FREQ_MASK; in vlv_write_infoframe()
335 val |= VIDEO_DIP_FREQ_VSYNC; in vlv_write_infoframe()
337 I915_WRITE(reg, val); in vlv_write_infoframe()
348 u32 val = I915_READ(reg); in vlv_infoframe_enabled() local
350 if ((val & VIDEO_DIP_ENABLE) == 0) in vlv_infoframe_enabled()
353 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) in vlv_infoframe_enabled()
356 return val & (VIDEO_DIP_ENABLE_AVI | in vlv_infoframe_enabled()
373 u32 val = I915_READ(ctl_reg); in hsw_write_infoframe() local
379 val &= ~hsw_infoframe_enable(type); in hsw_write_infoframe()
380 I915_WRITE(ctl_reg, val); in hsw_write_infoframe()
394 val |= hsw_infoframe_enable(type); in hsw_write_infoframe()
395 I915_WRITE(ctl_reg, val); in hsw_write_infoframe()
405 u32 val = I915_READ(ctl_reg); in hsw_infoframe_enabled() local
407 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | in hsw_infoframe_enabled()
517 u32 val = I915_READ(reg); in g4x_set_infoframes() local
531 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; in g4x_set_infoframes()
534 if (!(val & VIDEO_DIP_ENABLE)) in g4x_set_infoframes()
536 if (port != (val & VIDEO_DIP_PORT_MASK)) { in g4x_set_infoframes()
538 (val & VIDEO_DIP_PORT_MASK) >> 29); in g4x_set_infoframes()
541 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | in g4x_set_infoframes()
543 I915_WRITE(reg, val); in g4x_set_infoframes()
548 if (port != (val & VIDEO_DIP_PORT_MASK)) { in g4x_set_infoframes()
549 if (val & VIDEO_DIP_ENABLE) { in g4x_set_infoframes()
551 (val & VIDEO_DIP_PORT_MASK) >> 29); in g4x_set_infoframes()
554 val &= ~VIDEO_DIP_PORT_MASK; in g4x_set_infoframes()
555 val |= port; in g4x_set_infoframes()
558 val |= VIDEO_DIP_ENABLE; in g4x_set_infoframes()
559 val &= ~(VIDEO_DIP_ENABLE_AVI | in g4x_set_infoframes()
562 I915_WRITE(reg, val); in g4x_set_infoframes()
636 u32 reg, val = 0; in intel_hdmi_set_gcp_infoframe() local
649 val |= GCP_COLOR_INDICATION; in intel_hdmi_set_gcp_infoframe()
654 val |= GCP_DEFAULT_PHASE_ENABLE; in intel_hdmi_set_gcp_infoframe()
656 I915_WRITE(reg, val); in intel_hdmi_set_gcp_infoframe()
658 return val != 0; in intel_hdmi_set_gcp_infoframe()
670 u32 val = I915_READ(reg); in ibx_set_infoframes() local
676 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; in ibx_set_infoframes()
679 if (!(val & VIDEO_DIP_ENABLE)) in ibx_set_infoframes()
681 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | in ibx_set_infoframes()
684 I915_WRITE(reg, val); in ibx_set_infoframes()
689 if (port != (val & VIDEO_DIP_PORT_MASK)) { in ibx_set_infoframes()
690 WARN(val & VIDEO_DIP_ENABLE, in ibx_set_infoframes()
692 (val & VIDEO_DIP_PORT_MASK) >> 29); in ibx_set_infoframes()
693 val &= ~VIDEO_DIP_PORT_MASK; in ibx_set_infoframes()
694 val |= port; in ibx_set_infoframes()
697 val |= VIDEO_DIP_ENABLE; in ibx_set_infoframes()
698 val &= ~(VIDEO_DIP_ENABLE_AVI | in ibx_set_infoframes()
703 val |= VIDEO_DIP_ENABLE_GCP; in ibx_set_infoframes()
705 I915_WRITE(reg, val); in ibx_set_infoframes()
721 u32 val = I915_READ(reg); in cpt_set_infoframes() local
726 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; in cpt_set_infoframes()
729 if (!(val & VIDEO_DIP_ENABLE)) in cpt_set_infoframes()
731 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | in cpt_set_infoframes()
734 I915_WRITE(reg, val); in cpt_set_infoframes()
740 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; in cpt_set_infoframes()
741 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | in cpt_set_infoframes()
745 val |= VIDEO_DIP_ENABLE_GCP; in cpt_set_infoframes()
747 I915_WRITE(reg, val); in cpt_set_infoframes()
764 u32 val = I915_READ(reg); in vlv_set_infoframes() local
770 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; in vlv_set_infoframes()
773 if (!(val & VIDEO_DIP_ENABLE)) in vlv_set_infoframes()
775 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | in vlv_set_infoframes()
778 I915_WRITE(reg, val); in vlv_set_infoframes()
783 if (port != (val & VIDEO_DIP_PORT_MASK)) { in vlv_set_infoframes()
784 WARN(val & VIDEO_DIP_ENABLE, in vlv_set_infoframes()
786 (val & VIDEO_DIP_PORT_MASK) >> 29); in vlv_set_infoframes()
787 val &= ~VIDEO_DIP_PORT_MASK; in vlv_set_infoframes()
788 val |= port; in vlv_set_infoframes()
791 val |= VIDEO_DIP_ENABLE; in vlv_set_infoframes()
792 val &= ~(VIDEO_DIP_ENABLE_AVI | in vlv_set_infoframes()
797 val |= VIDEO_DIP_ENABLE_GCP; in vlv_set_infoframes()
799 I915_WRITE(reg, val); in vlv_set_infoframes()
815 u32 val = I915_READ(reg); in hsw_set_infoframes() local
819 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | in hsw_set_infoframes()
824 I915_WRITE(reg, val); in hsw_set_infoframes()
830 val |= VIDEO_DIP_ENABLE_GCP_HSW; in hsw_set_infoframes()
832 I915_WRITE(reg, val); in hsw_set_infoframes()
1461 uint64_t val) in intel_hdmi_set_property() argument
1469 ret = drm_object_property_set_value(&connector->base, property, val); in intel_hdmi_set_property()
1474 enum hdmi_force_audio i = val; in intel_hdmi_set_property()
1498 switch (val) { in intel_hdmi_set_property()
1522 switch (val) { in intel_hdmi_set_property()
1571 u32 val; in vlv_hdmi_pre_enable() local
1575 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); in vlv_hdmi_pre_enable()
1576 val = 0; in vlv_hdmi_pre_enable()
1578 val |= (1<<21); in vlv_hdmi_pre_enable()
1580 val &= ~(1<<21); in vlv_hdmi_pre_enable()
1581 val |= 0x001000c4; in vlv_hdmi_pre_enable()
1582 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); in vlv_hdmi_pre_enable()
1648 uint32_t val; in chv_data_lane_soft_reset() local
1650 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); in chv_data_lane_soft_reset()
1652 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); in chv_data_lane_soft_reset()
1654 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; in chv_data_lane_soft_reset()
1655 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); in chv_data_lane_soft_reset()
1658 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); in chv_data_lane_soft_reset()
1660 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); in chv_data_lane_soft_reset()
1662 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; in chv_data_lane_soft_reset()
1663 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); in chv_data_lane_soft_reset()
1666 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); in chv_data_lane_soft_reset()
1667 val |= CHV_PCS_REQ_SOFTRESET_EN; in chv_data_lane_soft_reset()
1669 val &= ~DPIO_PCS_CLK_SOFT_RESET; in chv_data_lane_soft_reset()
1671 val |= DPIO_PCS_CLK_SOFT_RESET; in chv_data_lane_soft_reset()
1672 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); in chv_data_lane_soft_reset()
1675 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); in chv_data_lane_soft_reset()
1676 val |= CHV_PCS_REQ_SOFTRESET_EN; in chv_data_lane_soft_reset()
1678 val &= ~DPIO_PCS_CLK_SOFT_RESET; in chv_data_lane_soft_reset()
1680 val |= DPIO_PCS_CLK_SOFT_RESET; in chv_data_lane_soft_reset()
1681 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); in chv_data_lane_soft_reset()
1694 u32 val; in chv_hdmi_pre_pll_enable() local
1715 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_hdmi_pre_pll_enable()
1716 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); in chv_hdmi_pre_pll_enable()
1718 val |= CHV_BUFLEFTENA1_FORCE; in chv_hdmi_pre_pll_enable()
1720 val |= CHV_BUFRIGHTENA1_FORCE; in chv_hdmi_pre_pll_enable()
1721 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); in chv_hdmi_pre_pll_enable()
1723 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); in chv_hdmi_pre_pll_enable()
1724 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); in chv_hdmi_pre_pll_enable()
1726 val |= CHV_BUFLEFTENA2_FORCE; in chv_hdmi_pre_pll_enable()
1728 val |= CHV_BUFRIGHTENA2_FORCE; in chv_hdmi_pre_pll_enable()
1729 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); in chv_hdmi_pre_pll_enable()
1733 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); in chv_hdmi_pre_pll_enable()
1734 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; in chv_hdmi_pre_pll_enable()
1736 val &= ~CHV_PCS_USEDCLKCHANNEL; in chv_hdmi_pre_pll_enable()
1738 val |= CHV_PCS_USEDCLKCHANNEL; in chv_hdmi_pre_pll_enable()
1739 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); in chv_hdmi_pre_pll_enable()
1741 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); in chv_hdmi_pre_pll_enable()
1742 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; in chv_hdmi_pre_pll_enable()
1744 val &= ~CHV_PCS_USEDCLKCHANNEL; in chv_hdmi_pre_pll_enable()
1746 val |= CHV_PCS_USEDCLKCHANNEL; in chv_hdmi_pre_pll_enable()
1747 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); in chv_hdmi_pre_pll_enable()
1754 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); in chv_hdmi_pre_pll_enable()
1756 val &= ~CHV_CMN_USEDCLKCHANNEL; in chv_hdmi_pre_pll_enable()
1758 val |= CHV_CMN_USEDCLKCHANNEL; in chv_hdmi_pre_pll_enable()
1759 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); in chv_hdmi_pre_pll_enable()
1768 u32 val; in chv_hdmi_post_pll_disable() local
1774 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_hdmi_post_pll_disable()
1775 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); in chv_hdmi_post_pll_disable()
1776 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); in chv_hdmi_post_pll_disable()
1778 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); in chv_hdmi_post_pll_disable()
1779 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); in chv_hdmi_post_pll_disable()
1780 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); in chv_hdmi_post_pll_disable()
1838 u32 val; in chv_hdmi_pre_enable() local
1843 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); in chv_hdmi_pre_enable()
1844 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; in chv_hdmi_pre_enable()
1845 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); in chv_hdmi_pre_enable()
1847 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); in chv_hdmi_pre_enable()
1848 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; in chv_hdmi_pre_enable()
1849 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); in chv_hdmi_pre_enable()
1871 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); in chv_hdmi_pre_enable()
1872 val |= DPIO_TX2_STAGGER_MASK(0x1f); in chv_hdmi_pre_enable()
1873 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); in chv_hdmi_pre_enable()
1875 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); in chv_hdmi_pre_enable()
1876 val |= DPIO_TX2_STAGGER_MASK(0x1f); in chv_hdmi_pre_enable()
1877 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); in chv_hdmi_pre_enable()
1897 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); in chv_hdmi_pre_enable()
1898 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); in chv_hdmi_pre_enable()
1899 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); in chv_hdmi_pre_enable()
1900 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; in chv_hdmi_pre_enable()
1901 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); in chv_hdmi_pre_enable()
1903 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); in chv_hdmi_pre_enable()
1904 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); in chv_hdmi_pre_enable()
1905 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); in chv_hdmi_pre_enable()
1906 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; in chv_hdmi_pre_enable()
1907 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); in chv_hdmi_pre_enable()
1909 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); in chv_hdmi_pre_enable()
1910 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); in chv_hdmi_pre_enable()
1911 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; in chv_hdmi_pre_enable()
1912 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); in chv_hdmi_pre_enable()
1914 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); in chv_hdmi_pre_enable()
1915 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); in chv_hdmi_pre_enable()
1916 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; in chv_hdmi_pre_enable()
1917 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); in chv_hdmi_pre_enable()
1922 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); in chv_hdmi_pre_enable()
1923 val &= ~DPIO_SWING_DEEMPH9P5_MASK; in chv_hdmi_pre_enable()
1924 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT; in chv_hdmi_pre_enable()
1925 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); in chv_hdmi_pre_enable()
1929 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); in chv_hdmi_pre_enable()
1931 val &= ~DPIO_SWING_MARGIN000_MASK; in chv_hdmi_pre_enable()
1932 val |= 102 << DPIO_SWING_MARGIN000_SHIFT; in chv_hdmi_pre_enable()
1939 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); in chv_hdmi_pre_enable()
1940 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; in chv_hdmi_pre_enable()
1942 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); in chv_hdmi_pre_enable()
1952 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); in chv_hdmi_pre_enable()
1953 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; in chv_hdmi_pre_enable()
1954 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); in chv_hdmi_pre_enable()
1958 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); in chv_hdmi_pre_enable()
1959 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; in chv_hdmi_pre_enable()
1960 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); in chv_hdmi_pre_enable()
1962 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); in chv_hdmi_pre_enable()
1963 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; in chv_hdmi_pre_enable()
1964 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); in chv_hdmi_pre_enable()