Lines Matching refs:pipe
196 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); in ibx_write_infoframe()
210 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); in ibx_write_infoframe()
215 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); in ibx_write_infoframe()
232 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); in ibx_infoframe_enabled()
254 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); in cpt_write_infoframe()
271 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); in cpt_write_infoframe()
276 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); in cpt_write_infoframe()
292 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); in cpt_infoframe_enabled()
311 int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); in vlv_write_infoframe()
325 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); in vlv_write_infoframe()
330 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); in vlv_write_infoframe()
347 int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); in vlv_infoframe_enabled()
641 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); in intel_hdmi_set_gcp_infoframe()
643 reg = TVIDEO_DIP_GCP(crtc->pipe); in intel_hdmi_set_gcp_infoframe()
669 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); in ibx_set_infoframes()
720 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); in cpt_set_infoframes()
763 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); in vlv_set_infoframes()
866 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); in intel_hdmi_prepare()
868 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); in intel_hdmi_prepare()
870 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); in intel_hdmi_prepare()
877 enum pipe *pipe) in intel_hdmi_get_hw_state() argument
895 *pipe = PORT_TO_PIPE_CPT(tmp); in intel_hdmi_get_hw_state()
897 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); in intel_hdmi_get_hw_state()
899 *pipe = PORT_TO_PIPE(tmp); in intel_hdmi_get_hw_state()
960 pipe_name(crtc->pipe)); in intel_enable_hdmi_audio()
1040 enum pipe pipe = crtc->pipe; in cpt_enable_hdmi() local
1060 I915_WRITE(TRANS_CHICKEN1(pipe), in cpt_enable_hdmi()
1061 I915_READ(TRANS_CHICKEN1(pipe)) | in cpt_enable_hdmi()
1078 I915_WRITE(TRANS_CHICKEN1(pipe), in cpt_enable_hdmi()
1079 I915_READ(TRANS_CHICKEN1(pipe)) & in cpt_enable_hdmi()
1110 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) { in intel_disable_hdmi()
1570 int pipe = intel_crtc->pipe; in vlv_hdmi_pre_enable() local
1575 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); in vlv_hdmi_pre_enable()
1577 if (pipe) in vlv_hdmi_pre_enable()
1582 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); in vlv_hdmi_pre_enable()
1585 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); in vlv_hdmi_pre_enable()
1586 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); in vlv_hdmi_pre_enable()
1587 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); in vlv_hdmi_pre_enable()
1588 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); in vlv_hdmi_pre_enable()
1589 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); in vlv_hdmi_pre_enable()
1590 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); in vlv_hdmi_pre_enable()
1591 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); in vlv_hdmi_pre_enable()
1592 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); in vlv_hdmi_pre_enable()
1595 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); in vlv_hdmi_pre_enable()
1596 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); in vlv_hdmi_pre_enable()
1616 int pipe = intel_crtc->pipe; in vlv_hdmi_pre_pll_enable() local
1622 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), in vlv_hdmi_pre_pll_enable()
1625 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), in vlv_hdmi_pre_pll_enable()
1632 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); in vlv_hdmi_pre_pll_enable()
1633 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); in vlv_hdmi_pre_pll_enable()
1634 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); in vlv_hdmi_pre_pll_enable()
1636 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); in vlv_hdmi_pre_pll_enable()
1637 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); in vlv_hdmi_pre_pll_enable()
1647 enum pipe pipe = crtc->pipe; in chv_data_lane_soft_reset() local
1650 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); in chv_data_lane_soft_reset()
1655 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); in chv_data_lane_soft_reset()
1658 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); in chv_data_lane_soft_reset()
1663 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); in chv_data_lane_soft_reset()
1666 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); in chv_data_lane_soft_reset()
1672 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); in chv_data_lane_soft_reset()
1675 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); in chv_data_lane_soft_reset()
1681 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); in chv_data_lane_soft_reset()
1693 enum pipe pipe = intel_crtc->pipe; in chv_hdmi_pre_pll_enable() local
1702 if (ch == DPIO_CH0 && pipe == PIPE_B) in chv_hdmi_pre_pll_enable()
1714 if (pipe != PIPE_B) { in chv_hdmi_pre_pll_enable()
1715 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_hdmi_pre_pll_enable()
1721 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); in chv_hdmi_pre_pll_enable()
1723 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); in chv_hdmi_pre_pll_enable()
1729 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); in chv_hdmi_pre_pll_enable()
1733 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); in chv_hdmi_pre_pll_enable()
1735 if (pipe != PIPE_B) in chv_hdmi_pre_pll_enable()
1739 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); in chv_hdmi_pre_pll_enable()
1741 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); in chv_hdmi_pre_pll_enable()
1743 if (pipe != PIPE_B) in chv_hdmi_pre_pll_enable()
1747 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); in chv_hdmi_pre_pll_enable()
1754 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); in chv_hdmi_pre_pll_enable()
1755 if (pipe != PIPE_B) in chv_hdmi_pre_pll_enable()
1759 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); in chv_hdmi_pre_pll_enable()
1767 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; in chv_hdmi_post_pll_disable() local
1773 if (pipe != PIPE_B) { in chv_hdmi_post_pll_disable()
1774 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_hdmi_post_pll_disable()
1776 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); in chv_hdmi_post_pll_disable()
1778 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); in chv_hdmi_post_pll_disable()
1780 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); in chv_hdmi_post_pll_disable()
1804 int pipe = intel_crtc->pipe; in vlv_hdmi_post_disable() local
1808 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); in vlv_hdmi_post_disable()
1809 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); in vlv_hdmi_post_disable()
1836 int pipe = intel_crtc->pipe; in chv_hdmi_pre_enable() local
1843 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); in chv_hdmi_pre_enable()
1845 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); in chv_hdmi_pre_enable()
1847 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); in chv_hdmi_pre_enable()
1849 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); in chv_hdmi_pre_enable()
1855 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), in chv_hdmi_pre_enable()
1871 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); in chv_hdmi_pre_enable()
1873 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); in chv_hdmi_pre_enable()
1875 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); in chv_hdmi_pre_enable()
1877 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); in chv_hdmi_pre_enable()
1879 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), in chv_hdmi_pre_enable()
1886 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), in chv_hdmi_pre_enable()
1897 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); in chv_hdmi_pre_enable()
1901 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); in chv_hdmi_pre_enable()
1903 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); in chv_hdmi_pre_enable()
1907 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); in chv_hdmi_pre_enable()
1909 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); in chv_hdmi_pre_enable()
1912 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); in chv_hdmi_pre_enable()
1914 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); in chv_hdmi_pre_enable()
1917 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); in chv_hdmi_pre_enable()
1922 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); in chv_hdmi_pre_enable()
1925 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); in chv_hdmi_pre_enable()
1929 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); in chv_hdmi_pre_enable()
1942 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); in chv_hdmi_pre_enable()
1952 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); in chv_hdmi_pre_enable()
1954 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); in chv_hdmi_pre_enable()
1958 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); in chv_hdmi_pre_enable()
1960 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); in chv_hdmi_pre_enable()
1962 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); in chv_hdmi_pre_enable()
1964 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); in chv_hdmi_pre_enable()