Lines Matching refs:dev_priv
50 struct drm_i915_private *dev_priv = dev->dev_private; in assert_hdmi_port_disabled() local
116 static u32 hsw_dip_data_reg(struct drm_i915_private *dev_priv, in hsw_dip_data_reg() argument
140 struct drm_i915_private *dev_priv = dev->dev_private; in g4x_write_infoframe() local
174 struct drm_i915_private *dev_priv = dev->dev_private; in g4x_infoframe_enabled() local
194 struct drm_i915_private *dev_priv = dev->dev_private; in ibx_write_infoframe() local
229 struct drm_i915_private *dev_priv = dev->dev_private; in ibx_infoframe_enabled() local
252 struct drm_i915_private *dev_priv = dev->dev_private; in cpt_write_infoframe() local
290 struct drm_i915_private *dev_priv = dev->dev_private; in cpt_infoframe_enabled() local
309 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_write_infoframe() local
344 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_infoframe_enabled() local
367 struct drm_i915_private *dev_priv = dev->dev_private; in hsw_write_infoframe() local
375 data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0); in hsw_write_infoframe()
384 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, in hsw_write_infoframe()
390 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, in hsw_write_infoframe()
402 struct drm_i915_private *dev_priv = dev->dev_private; in hsw_infoframe_enabled() local
513 struct drm_i915_private *dev_priv = encoder->dev->dev_private; in g4x_set_infoframes() local
634 struct drm_i915_private *dev_priv = encoder->dev->dev_private; in intel_hdmi_set_gcp_infoframe() local
638 if (HAS_DDI(dev_priv)) in intel_hdmi_set_gcp_infoframe()
640 else if (IS_VALLEYVIEW(dev_priv)) in intel_hdmi_set_gcp_infoframe()
642 else if (HAS_PCH_SPLIT(dev_priv->dev)) in intel_hdmi_set_gcp_infoframe()
665 struct drm_i915_private *dev_priv = encoder->dev->dev_private; in ibx_set_infoframes() local
717 struct drm_i915_private *dev_priv = encoder->dev->dev_private; in cpt_set_infoframes() local
759 struct drm_i915_private *dev_priv = encoder->dev->dev_private; in vlv_set_infoframes() local
811 struct drm_i915_private *dev_priv = encoder->dev->dev_private; in hsw_set_infoframes() local
843 struct drm_i915_private *dev_priv = dev->dev_private; in intel_hdmi_prepare() local
880 struct drm_i915_private *dev_priv = dev->dev_private; in intel_hdmi_get_hw_state() local
886 if (!intel_display_power_is_enabled(dev_priv, power_domain)) in intel_hdmi_get_hw_state()
909 struct drm_i915_private *dev_priv = dev->dev_private; in intel_hdmi_get_config() local
948 if (HAS_PCH_SPLIT(dev_priv->dev)) in intel_hdmi_get_config()
967 struct drm_i915_private *dev_priv = dev->dev_private; in g4x_enable_hdmi() local
988 struct drm_i915_private *dev_priv = dev->dev_private; in ibx_enable_hdmi() local
1037 struct drm_i915_private *dev_priv = dev->dev_private; in cpt_enable_hdmi() local
1094 struct drm_i915_private *dev_priv = dev->dev_private; in intel_disable_hdmi() local
1336 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_hdmi_set_edid() local
1341 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); in intel_hdmi_set_edid()
1345 intel_gmbus_get_adapter(dev_priv, in intel_hdmi_set_edid()
1348 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); in intel_hdmi_set_edid()
1375 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_hdmi_detect() local
1382 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); in intel_hdmi_detect()
1387 live_status = intel_digital_port_connected(dev_priv, in intel_hdmi_detect()
1398 if (INTEL_INFO(dev_priv)->gen < 7 || IS_IVYBRIDGE(dev_priv)) in intel_hdmi_detect()
1412 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); in intel_hdmi_detect()
1466 struct drm_i915_private *dev_priv = connector->dev->dev_private; in intel_hdmi_set_property() local
1473 if (property == dev_priv->force_audio_property) { in intel_hdmi_set_property()
1494 if (property == dev_priv->broadcast_rgb_property) { in intel_hdmi_set_property()
1565 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_hdmi_pre_enable() local
1574 mutex_lock(&dev_priv->sb_lock); in vlv_hdmi_pre_enable()
1575 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); in vlv_hdmi_pre_enable()
1582 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); in vlv_hdmi_pre_enable()
1585 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); in vlv_hdmi_pre_enable()
1586 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); in vlv_hdmi_pre_enable()
1587 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); in vlv_hdmi_pre_enable()
1588 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); in vlv_hdmi_pre_enable()
1589 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); in vlv_hdmi_pre_enable()
1590 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); in vlv_hdmi_pre_enable()
1591 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); in vlv_hdmi_pre_enable()
1592 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); in vlv_hdmi_pre_enable()
1595 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); in vlv_hdmi_pre_enable()
1596 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); in vlv_hdmi_pre_enable()
1597 mutex_unlock(&dev_priv->sb_lock); in vlv_hdmi_pre_enable()
1605 vlv_wait_port_ready(dev_priv, dport, 0x0); in vlv_hdmi_pre_enable()
1612 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_hdmi_pre_pll_enable() local
1621 mutex_lock(&dev_priv->sb_lock); in vlv_hdmi_pre_pll_enable()
1622 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), in vlv_hdmi_pre_pll_enable()
1625 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), in vlv_hdmi_pre_pll_enable()
1632 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); in vlv_hdmi_pre_pll_enable()
1633 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); in vlv_hdmi_pre_pll_enable()
1634 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); in vlv_hdmi_pre_pll_enable()
1636 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); in vlv_hdmi_pre_pll_enable()
1637 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); in vlv_hdmi_pre_pll_enable()
1638 mutex_unlock(&dev_priv->sb_lock); in vlv_hdmi_pre_pll_enable()
1644 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_data_lane_soft_reset() local
1650 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); in chv_data_lane_soft_reset()
1655 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); in chv_data_lane_soft_reset()
1658 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); in chv_data_lane_soft_reset()
1663 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); in chv_data_lane_soft_reset()
1666 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); in chv_data_lane_soft_reset()
1672 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); in chv_data_lane_soft_reset()
1675 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); in chv_data_lane_soft_reset()
1681 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); in chv_data_lane_soft_reset()
1689 struct drm_i915_private *dev_priv = dev->dev_private; in chv_hdmi_pre_pll_enable() local
1704 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); in chv_hdmi_pre_pll_enable()
1708 mutex_lock(&dev_priv->sb_lock); in chv_hdmi_pre_pll_enable()
1715 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_hdmi_pre_pll_enable()
1721 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); in chv_hdmi_pre_pll_enable()
1723 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); in chv_hdmi_pre_pll_enable()
1729 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); in chv_hdmi_pre_pll_enable()
1733 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); in chv_hdmi_pre_pll_enable()
1739 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); in chv_hdmi_pre_pll_enable()
1741 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); in chv_hdmi_pre_pll_enable()
1747 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); in chv_hdmi_pre_pll_enable()
1754 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); in chv_hdmi_pre_pll_enable()
1759 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); in chv_hdmi_pre_pll_enable()
1761 mutex_unlock(&dev_priv->sb_lock); in chv_hdmi_pre_pll_enable()
1766 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_hdmi_post_pll_disable() local
1770 mutex_lock(&dev_priv->sb_lock); in chv_hdmi_post_pll_disable()
1774 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_hdmi_post_pll_disable()
1776 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); in chv_hdmi_post_pll_disable()
1778 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); in chv_hdmi_post_pll_disable()
1780 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); in chv_hdmi_post_pll_disable()
1783 mutex_unlock(&dev_priv->sb_lock); in chv_hdmi_post_pll_disable()
1800 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; in vlv_hdmi_post_disable() local
1807 mutex_lock(&dev_priv->sb_lock); in vlv_hdmi_post_disable()
1808 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); in vlv_hdmi_post_disable()
1809 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); in vlv_hdmi_post_disable()
1810 mutex_unlock(&dev_priv->sb_lock); in vlv_hdmi_post_disable()
1816 struct drm_i915_private *dev_priv = dev->dev_private; in chv_hdmi_post_disable() local
1818 mutex_lock(&dev_priv->sb_lock); in chv_hdmi_post_disable()
1823 mutex_unlock(&dev_priv->sb_lock); in chv_hdmi_post_disable()
1831 struct drm_i915_private *dev_priv = dev->dev_private; in chv_hdmi_pre_enable() local
1840 mutex_lock(&dev_priv->sb_lock); in chv_hdmi_pre_enable()
1843 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); in chv_hdmi_pre_enable()
1845 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); in chv_hdmi_pre_enable()
1847 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); in chv_hdmi_pre_enable()
1849 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); in chv_hdmi_pre_enable()
1855 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), in chv_hdmi_pre_enable()
1871 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); in chv_hdmi_pre_enable()
1873 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); in chv_hdmi_pre_enable()
1875 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); in chv_hdmi_pre_enable()
1877 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); in chv_hdmi_pre_enable()
1879 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), in chv_hdmi_pre_enable()
1886 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), in chv_hdmi_pre_enable()
1897 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); in chv_hdmi_pre_enable()
1901 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); in chv_hdmi_pre_enable()
1903 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); in chv_hdmi_pre_enable()
1907 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); in chv_hdmi_pre_enable()
1909 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); in chv_hdmi_pre_enable()
1912 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); in chv_hdmi_pre_enable()
1914 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); in chv_hdmi_pre_enable()
1917 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); in chv_hdmi_pre_enable()
1922 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); in chv_hdmi_pre_enable()
1925 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); in chv_hdmi_pre_enable()
1929 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); in chv_hdmi_pre_enable()
1942 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); in chv_hdmi_pre_enable()
1952 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); in chv_hdmi_pre_enable()
1954 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); in chv_hdmi_pre_enable()
1958 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); in chv_hdmi_pre_enable()
1960 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); in chv_hdmi_pre_enable()
1962 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); in chv_hdmi_pre_enable()
1964 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); in chv_hdmi_pre_enable()
1966 mutex_unlock(&dev_priv->sb_lock); in chv_hdmi_pre_enable()
1974 vlv_wait_port_ready(dev_priv, dport, 0x0); in chv_hdmi_pre_enable()
1978 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); in chv_hdmi_pre_enable()
2029 struct drm_i915_private *dev_priv = dev->dev_private; in intel_hdmi_init_connector() local
2043 if (IS_BROXTON(dev_priv)) in intel_hdmi_init_connector()
2051 if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) in intel_hdmi_init_connector()
2057 if (IS_BROXTON(dev_priv)) in intel_hdmi_init_connector()
2064 if (WARN_ON(IS_BROXTON(dev_priv))) in intel_hdmi_init_connector()
2066 else if (IS_CHERRYVIEW(dev_priv)) in intel_hdmi_init_connector()
2076 dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin; in intel_hdmi_init_connector()