728 struct intel_dp {  struct
729 	uint32_t output_reg;
730 	uint32_t aux_ch_ctl_reg;
731 	uint32_t DP;
732 	int link_rate;
733 	uint8_t lane_count;
734 	bool has_audio;
735 	enum hdmi_force_audio force_audio;
736 	bool limited_color_range;
737 	bool color_range_auto;
738 	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
739 	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
740 	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
742 	uint8_t num_sink_rates;
743 	int sink_rates[DP_MAX_SUPPORTED_RATES];
744 	struct sink_crc sink_crc;
745 	struct drm_dp_aux aux;
746 	uint8_t train_set[4];
747 	int panel_power_up_delay;
748 	int panel_power_down_delay;
749 	int panel_power_cycle_delay;
750 	int backlight_on_delay;
774 	struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];  argument
777 	uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);  argument
782 	uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,  argument
798 	struct intel_dp dp;  argument
915 dp_to_dig_port(struct intel_dp *intel_dp)  in dp_to_dig_port()