34 					struct intel_crtc_state *pipe_config)  in intel_dp_mst_compute_config()  argument
43 	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;  in intel_dp_mst_compute_config()
49 	pipe_config->dp_encoder_is_mst = true;  in intel_dp_mst_compute_config()
50 	pipe_config->has_pch_encoder = false;  in intel_dp_mst_compute_config()
51 	pipe_config->has_dp_encoder = true;  in intel_dp_mst_compute_config()
60 	pipe_config->lane_count = lane_count;  in intel_dp_mst_compute_config()
62 	pipe_config->pipe_bpp = 24;  in intel_dp_mst_compute_config()
63 	pipe_config->port_clock = intel_dp_max_link_rate(intel_dp);  in intel_dp_mst_compute_config()
65 	state = pipe_config->base.state;  in intel_dp_mst_compute_config()
83 	pipe_config->pbn = mst_pbn;  in intel_dp_mst_compute_config()
88 			       pipe_config->port_clock,  in intel_dp_mst_compute_config()
89 			       &pipe_config->dp_m_n);  in intel_dp_mst_compute_config()
91 	pipe_config->dp_m_n.tu = slots;  in intel_dp_mst_compute_config()
94 		hsw_dp_set_ddi_pll_sel(pipe_config);  in intel_dp_mst_compute_config()
242 					struct intel_crtc_state *pipe_config)  in intel_dp_mst_enc_get_config()  argument
249 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;  in intel_dp_mst_enc_get_config()
252 	pipe_config->has_dp_encoder = true;  in intel_dp_mst_enc_get_config()
266 		pipe_config->pipe_bpp = 18;  in intel_dp_mst_enc_get_config()
269 		pipe_config->pipe_bpp = 24;  in intel_dp_mst_enc_get_config()
272 		pipe_config->pipe_bpp = 30;  in intel_dp_mst_enc_get_config()
275 		pipe_config->pipe_bpp = 36;  in intel_dp_mst_enc_get_config()
280 	pipe_config->base.adjusted_mode.flags |= flags;  in intel_dp_mst_enc_get_config()
282 	pipe_config->lane_count =  in intel_dp_mst_enc_get_config()
285 	intel_dp_get_m_n(crtc, pipe_config);  in intel_dp_mst_enc_get_config()
287 	intel_ddi_clock_get(&intel_dig_port->base, pipe_config);  in intel_dp_mst_enc_get_config()