3456 	uint32_t	signal_levels = 0;  in gen4_signal_levels()  local
3461 		signal_levels |= DP_VOLTAGE_0_4;  in gen4_signal_levels()
3464 		signal_levels |= DP_VOLTAGE_0_6;  in gen4_signal_levels()
3467 		signal_levels |= DP_VOLTAGE_0_8;  in gen4_signal_levels()
3470 		signal_levels |= DP_VOLTAGE_1_2;  in gen4_signal_levels()
3476 		signal_levels |= DP_PRE_EMPHASIS_0;  in gen4_signal_levels()
3479 		signal_levels |= DP_PRE_EMPHASIS_3_5;  in gen4_signal_levels()
3482 		signal_levels |= DP_PRE_EMPHASIS_6;  in gen4_signal_levels()
3485 		signal_levels |= DP_PRE_EMPHASIS_9_5;  in gen4_signal_levels()
3488 	return signal_levels;  in gen4_signal_levels()
3495 	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |  in gen6_edp_signal_levels()  local
3497 	switch (signal_levels) {  in gen6_edp_signal_levels()
3514 			      "0x%x\n", signal_levels);  in gen6_edp_signal_levels()
3523 	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |  in gen7_edp_signal_levels()  local
3525 	switch (signal_levels) {  in gen7_edp_signal_levels()
3545 			      "0x%x\n", signal_levels);  in gen7_edp_signal_levels()
3557 	uint32_t signal_levels, mask = 0;  in intel_dp_set_signal_levels()  local
3561 		signal_levels = ddi_signal_levels(intel_dp);  in intel_dp_set_signal_levels()
3564 			signal_levels = 0;  in intel_dp_set_signal_levels()
3568 		signal_levels = chv_signal_levels(intel_dp);  in intel_dp_set_signal_levels()
3570 		signal_levels = vlv_signal_levels(intel_dp);  in intel_dp_set_signal_levels()
3572 		signal_levels = gen7_edp_signal_levels(train_set);  in intel_dp_set_signal_levels()
3575 		signal_levels = gen6_edp_signal_levels(train_set);  in intel_dp_set_signal_levels()
3578 		signal_levels = gen4_signal_levels(train_set);  in intel_dp_set_signal_levels()
3583 		DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);  in intel_dp_set_signal_levels()
3591 	*DP = (*DP & ~mask) | signal_levels;  in intel_dp_set_signal_levels()