585 		u32 pp_ctrl_reg, pp_div_reg;  in edp_notify_handler()  local
588 		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);  in edp_notify_handler()
595 		I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);  in edp_notify_handler()
1680 	u32 pp_stat_reg, pp_ctrl_reg;  in wait_panel_status()  local
1685 	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);  in wait_panel_status()
1690 			I915_READ(pp_ctrl_reg));  in wait_panel_status()
1695 				I915_READ(pp_ctrl_reg));  in wait_panel_status()
1770 	u32 pp_stat_reg, pp_ctrl_reg;  in edp_panel_vdd_on()  local
1797 	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);  in edp_panel_vdd_on()
1799 	I915_WRITE(pp_ctrl_reg, pp);  in edp_panel_vdd_on()
1800 	POSTING_READ(pp_ctrl_reg);  in edp_panel_vdd_on()
1802 			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));  in edp_panel_vdd_on()
1846 	u32 pp_stat_reg, pp_ctrl_reg;  in edp_panel_vdd_off_sync()  local
1861 	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);  in edp_panel_vdd_off_sync()
1864 	I915_WRITE(pp_ctrl_reg, pp);  in edp_panel_vdd_off_sync()
1865 	POSTING_READ(pp_ctrl_reg);  in edp_panel_vdd_off_sync()
1869 	I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));  in edp_panel_vdd_off_sync()
1933 	u32 pp_ctrl_reg;  in edp_panel_on()  local
1950 	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);  in edp_panel_on()
1955 		I915_WRITE(pp_ctrl_reg, pp);  in edp_panel_on()
1956 		POSTING_READ(pp_ctrl_reg);  in edp_panel_on()
1963 	I915_WRITE(pp_ctrl_reg, pp);  in edp_panel_on()
1964 	POSTING_READ(pp_ctrl_reg);  in edp_panel_on()
1971 		I915_WRITE(pp_ctrl_reg, pp);  in edp_panel_on()
1972 		POSTING_READ(pp_ctrl_reg);  in edp_panel_on()
1995 	u32 pp_ctrl_reg;  in edp_panel_off()  local
2014 	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);  in edp_panel_off()
2018 	I915_WRITE(pp_ctrl_reg, pp);  in edp_panel_off()
2019 	POSTING_READ(pp_ctrl_reg);  in edp_panel_off()
2046 	u32 pp_ctrl_reg;  in _intel_edp_backlight_on()  local
2061 	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);  in _intel_edp_backlight_on()
2063 	I915_WRITE(pp_ctrl_reg, pp);  in _intel_edp_backlight_on()
2064 	POSTING_READ(pp_ctrl_reg);  in _intel_edp_backlight_on()
2087 	u32 pp_ctrl_reg;  in _intel_edp_backlight_off()  local
2097 	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);  in _intel_edp_backlight_off()
2099 	I915_WRITE(pp_ctrl_reg, pp);  in _intel_edp_backlight_off()
2100 	POSTING_READ(pp_ctrl_reg);  in _intel_edp_backlight_off()
5297 	int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg = 0;  in intel_dp_init_panel_power_sequencer()  local
5311 		pp_ctrl_reg = BXT_PP_CONTROL(0);  in intel_dp_init_panel_power_sequencer()
5315 		pp_ctrl_reg = PCH_PP_CONTROL;  in intel_dp_init_panel_power_sequencer()
5322 		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);  in intel_dp_init_panel_power_sequencer()
5335 		I915_WRITE(pp_ctrl_reg, pp_ctl);  in intel_dp_init_panel_power_sequencer()
5419 	int pp_on_reg, pp_off_reg, pp_div_reg = 0, pp_ctrl_reg;  in intel_dp_init_panel_power_sequencer_registers()  local
5431 		pp_ctrl_reg = BXT_PP_CONTROL(0);  in intel_dp_init_panel_power_sequencer_registers()
5462 		pp_div = I915_READ(pp_ctrl_reg);  in intel_dp_init_panel_power_sequencer_registers()
5488 		I915_WRITE(pp_ctrl_reg, pp_div);  in intel_dp_init_panel_power_sequencer_registers()
5496 		      (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :  in intel_dp_init_panel_power_sequencer_registers()