131 				      enum pipe pipe);
306 	enum pipe pipe = intel_dp->pps_pipe;  in vlv_power_sequencer_kick()  local
308 	enum dpio_phy phy = DPIO_PHY(pipe);  in vlv_power_sequencer_kick()
309 	enum dpio_channel ch = vlv_pipe_to_channel(pipe);  in vlv_power_sequencer_kick()
314 		 pipe_name(pipe), port_name(intel_dig_port->port)))  in vlv_power_sequencer_kick()
318 		      pipe_name(pipe), port_name(intel_dig_port->port));  in vlv_power_sequencer_kick()
329 		DP |= DP_PIPE_SELECT_CHV(pipe);  in vlv_power_sequencer_kick()
330 	else if (pipe == PIPE_B)  in vlv_power_sequencer_kick()
333 	pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;  in vlv_power_sequencer_kick()
343 		vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?  in vlv_power_sequencer_kick()
363 		vlv_force_pll_off(dev, pipe);  in vlv_power_sequencer_kick()
370 static enum pipe
378 	enum pipe pipe;  in vlv_power_sequencer_pipe()  local
410 		pipe = PIPE_A;  in vlv_power_sequencer_pipe()
412 		pipe = ffs(pipes) - 1;  in vlv_power_sequencer_pipe()
414 	vlv_steal_power_sequencer(dev, pipe);  in vlv_power_sequencer_pipe()
415 	intel_dp->pps_pipe = pipe;  in vlv_power_sequencer_pipe()
435 			       enum pipe pipe);
438 			       enum pipe pipe)  in vlv_pipe_has_pp_on()  argument
440 	return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;  in vlv_pipe_has_pp_on()
444 				enum pipe pipe)  in vlv_pipe_has_vdd_on()  argument
446 	return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;  in vlv_pipe_has_vdd_on()
450 			 enum pipe pipe)  in vlv_pipe_any()  argument
455 static enum pipe
460 	enum pipe pipe;  in vlv_initial_pps_pipe()  local
462 	for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {  in vlv_initial_pps_pipe()
463 		u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &  in vlv_initial_pps_pipe()
469 		if (!pipe_check(dev_priv, pipe))  in vlv_initial_pps_pipe()
472 		return pipe;  in vlv_initial_pps_pipe()
584 		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);  in edp_notify_handler()  local
588 		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);  in edp_notify_handler()
589 		pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);  in edp_notify_handler()
1632 		intel_dp->DP |= crtc->pipe << 29;  in intel_dp_prepare()
1638 		trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));  in intel_dp_prepare()
1643 		I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);  in intel_dp_prepare()
1659 			intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);  in intel_dp_prepare()
1660 		else if (crtc->pipe == PIPE_B)  in intel_dp_prepare()
2155 			     to_intel_crtc(crtc)->pipe);  in ironlake_edp_pll_on()
2181 			     to_intel_crtc(crtc)->pipe);  in ironlake_edp_pll_off()
2229 				  enum pipe *pipe)  in intel_dp_get_hw_state()  argument
2248 		*pipe = PORT_TO_PIPE_CPT(tmp);  in intel_dp_get_hw_state()
2250 		enum pipe p;  in intel_dp_get_hw_state()
2255 				*pipe = p;  in intel_dp_get_hw_state()
2263 		*pipe = DP_PORT_TO_PIPE_CHV(tmp);  in intel_dp_get_hw_state()
2265 		*pipe = PORT_TO_PIPE(tmp);  in intel_dp_get_hw_state()
2287 		u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));  in intel_dp_get_config()
2406 	enum pipe pipe = crtc->pipe;  in chv_data_lane_soft_reset()  local
2409 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));  in chv_data_lane_soft_reset()
2414 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);  in chv_data_lane_soft_reset()
2417 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));  in chv_data_lane_soft_reset()
2422 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);  in chv_data_lane_soft_reset()
2425 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));  in chv_data_lane_soft_reset()
2431 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);  in chv_data_lane_soft_reset()
2434 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));  in chv_data_lane_soft_reset()
2440 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);  in chv_data_lane_soft_reset()
2608 				 pipe_name(crtc->pipe));  in intel_enable_dp()
2647 	enum pipe pipe = intel_dp->pps_pipe;  in vlv_detach_power_sequencer()  local
2648 	int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);  in vlv_detach_power_sequencer()
2662 		      pipe_name(pipe), port_name(intel_dig_port->port));  in vlv_detach_power_sequencer()
2670 				      enum pipe pipe)  in vlv_steal_power_sequencer()  argument
2677 	if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))  in vlv_steal_power_sequencer()
2691 		if (intel_dp->pps_pipe != pipe)  in vlv_steal_power_sequencer()
2695 			      pipe_name(pipe), port_name(port));  in vlv_steal_power_sequencer()
2699 		     pipe_name(pipe), port_name(port));  in vlv_steal_power_sequencer()
2719 	if (intel_dp->pps_pipe == crtc->pipe)  in vlv_init_panel_power_sequencer()
2734 	vlv_steal_power_sequencer(dev, crtc->pipe);  in vlv_init_panel_power_sequencer()
2737 	intel_dp->pps_pipe = crtc->pipe;  in vlv_init_panel_power_sequencer()
2755 	int pipe = intel_crtc->pipe;  in vlv_pre_enable_dp()  local
2760 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));  in vlv_pre_enable_dp()
2762 	if (pipe)  in vlv_pre_enable_dp()
2767 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);  in vlv_pre_enable_dp()
2768 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);  in vlv_pre_enable_dp()
2769 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);  in vlv_pre_enable_dp()
2784 	int pipe = intel_crtc->pipe;  in vlv_dp_pre_pll_enable()  local
2790 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),  in vlv_dp_pre_pll_enable()
2793 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),  in vlv_dp_pre_pll_enable()
2800 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);  in vlv_dp_pre_pll_enable()
2801 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);  in vlv_dp_pre_pll_enable()
2802 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);  in vlv_dp_pre_pll_enable()
2815 	int pipe = intel_crtc->pipe;  in chv_pre_enable_dp()  local
2822 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));  in chv_pre_enable_dp()
2824 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);  in chv_pre_enable_dp()
2827 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));  in chv_pre_enable_dp()
2829 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);  in chv_pre_enable_dp()
2839 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),  in chv_pre_enable_dp()
2855 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));  in chv_pre_enable_dp()
2857 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);  in chv_pre_enable_dp()
2860 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));  in chv_pre_enable_dp()
2862 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);  in chv_pre_enable_dp()
2865 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),  in chv_pre_enable_dp()
2873 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),  in chv_pre_enable_dp()
2903 	enum pipe pipe = intel_crtc->pipe;  in chv_dp_pre_pll_enable()  local
2914 	if (ch == DPIO_CH0 && pipe == PIPE_B)  in chv_dp_pre_pll_enable()
2926 	if (pipe != PIPE_B) {  in chv_dp_pre_pll_enable()
2927 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);  in chv_dp_pre_pll_enable()
2933 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);  in chv_dp_pre_pll_enable()
2935 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);  in chv_dp_pre_pll_enable()
2941 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);  in chv_dp_pre_pll_enable()
2945 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));  in chv_dp_pre_pll_enable()
2947 	if (pipe != PIPE_B)  in chv_dp_pre_pll_enable()
2951 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);  in chv_dp_pre_pll_enable()
2954 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));  in chv_dp_pre_pll_enable()
2956 		if (pipe != PIPE_B)  in chv_dp_pre_pll_enable()
2960 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);  in chv_dp_pre_pll_enable()
2968 	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));  in chv_dp_pre_pll_enable()
2969 	if (pipe != PIPE_B)  in chv_dp_pre_pll_enable()
2973 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);  in chv_dp_pre_pll_enable()
2981 	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;  in chv_dp_post_pll_disable()  local
2987 	if (pipe != PIPE_B) {  in chv_dp_post_pll_disable()
2988 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);  in chv_dp_post_pll_disable()
2990 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);  in chv_dp_post_pll_disable()
2992 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);  in chv_dp_post_pll_disable()
2994 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);  in chv_dp_post_pll_disable()
3158 	int pipe = intel_crtc->pipe;  in vlv_signal_levels()  local
3234 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);  in vlv_signal_levels()
3235 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);  in vlv_signal_levels()
3236 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),  in vlv_signal_levels()
3238 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);  in vlv_signal_levels()
3239 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);  in vlv_signal_levels()
3240 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);  in vlv_signal_levels()
3241 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);  in vlv_signal_levels()
3262 	enum pipe pipe = intel_crtc->pipe;  in chv_signal_levels()  local
3338 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));  in chv_signal_levels()
3342 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);  in chv_signal_levels()
3345 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));  in chv_signal_levels()
3349 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);  in chv_signal_levels()
3352 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));  in chv_signal_levels()
3355 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);  in chv_signal_levels()
3358 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));  in chv_signal_levels()
3361 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);  in chv_signal_levels()
3366 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));  in chv_signal_levels()
3369 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);  in chv_signal_levels()
3374 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));  in chv_signal_levels()
3387 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);  in chv_signal_levels()
3397 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));  in chv_signal_levels()
3402 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);  in chv_signal_levels()
3406 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));  in chv_signal_levels()
3408 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);  in chv_signal_levels()
3411 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));  in chv_signal_levels()
3413 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);  in chv_signal_levels()
3956 	if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {  in intel_dp_link_down()
4180 		intel_wait_for_vblank(dev, intel_crtc->pipe);  in intel_dp_sink_crc()
5320 		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);  in intel_dp_init_panel_power_sequencer()  local
5322 		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);  in intel_dp_init_panel_power_sequencer()
5323 		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);  in intel_dp_init_panel_power_sequencer()
5324 		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);  in intel_dp_init_panel_power_sequencer()
5325 		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);  in intel_dp_init_panel_power_sequencer()
5440 		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);  in intel_dp_init_panel_power_sequencer_registers()  local
5442 		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);  in intel_dp_init_panel_power_sequencer_registers()
5443 		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);  in intel_dp_init_panel_power_sequencer_registers()
5444 		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);  in intel_dp_init_panel_power_sequencer_registers()
5715 	enum pipe pipe;  in intel_edp_drrs_invalidate()  local
5729 	pipe = to_intel_crtc(crtc)->pipe;  in intel_edp_drrs_invalidate()
5731 	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);  in intel_edp_drrs_invalidate()
5760 	enum pipe pipe;  in intel_edp_drrs_flush()  local
5774 	pipe = to_intel_crtc(crtc)->pipe;  in intel_edp_drrs_flush()
5776 	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);  in intel_edp_drrs_flush()
5895 	enum pipe pipe = INVALID_PIPE;  in intel_edp_init_connector()  local
5968 			pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);  in intel_edp_init_connector()
5970 			pipe = PORT_TO_PIPE(intel_dp->DP);  in intel_edp_init_connector()
5972 		if (pipe != PIPE_A && pipe != PIPE_B)  in intel_edp_init_connector()
5973 			pipe = intel_dp->pps_pipe;  in intel_edp_init_connector()
5975 		if (pipe != PIPE_A && pipe != PIPE_B)  in intel_edp_init_connector()
5976 			pipe = PIPE_A;  in intel_edp_init_connector()
5979 			      pipe_name(pipe));  in intel_edp_init_connector()
5984 	intel_panel_setup_backlight(connector, pipe);  in intel_edp_init_connector()