Lines Matching refs:dev_priv
273 struct drm_i915_private *dev_priv = dev->dev_private; in pps_lock() local
281 intel_display_power_get(dev_priv, power_domain); in pps_lock()
283 mutex_lock(&dev_priv->pps_mutex); in pps_lock()
291 struct drm_i915_private *dev_priv = dev->dev_private; in pps_unlock() local
294 mutex_unlock(&dev_priv->pps_mutex); in pps_unlock()
297 intel_display_power_put(dev_priv, power_domain); in pps_unlock()
305 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_power_sequencer_kick() local
341 !chv_phy_powergate_ch(dev_priv, phy, ch, true); in vlv_power_sequencer_kick()
366 chv_phy_powergate_ch(dev_priv, phy, ch, false); in vlv_power_sequencer_kick()
375 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_power_sequencer_pipe() local
380 lockdep_assert_held(&dev_priv->pps_mutex); in vlv_power_sequencer_pipe()
434 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
437 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, in vlv_pipe_has_pp_on() argument
443 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, in vlv_pipe_has_vdd_on() argument
449 static bool vlv_pipe_any(struct drm_i915_private *dev_priv, in vlv_pipe_any() argument
456 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, in vlv_initial_pps_pipe() argument
469 if (!pipe_check(dev_priv, pipe)) in vlv_initial_pps_pipe()
483 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_initial_power_sequencer_setup() local
486 lockdep_assert_held(&dev_priv->pps_mutex); in vlv_initial_power_sequencer_setup()
490 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, in vlv_initial_power_sequencer_setup()
494 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, in vlv_initial_power_sequencer_setup()
498 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, in vlv_initial_power_sequencer_setup()
515 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv) in vlv_power_sequencer_reset() argument
517 struct drm_device *dev = dev_priv->dev; in vlv_power_sequencer_reset()
576 struct drm_i915_private *dev_priv = dev->dev_private; in edp_notify_handler() local
607 struct drm_i915_private *dev_priv = dev->dev_private; in edp_have_panel_power() local
609 lockdep_assert_held(&dev_priv->pps_mutex); in edp_have_panel_power()
621 struct drm_i915_private *dev_priv = dev->dev_private; in edp_have_panel_vdd() local
623 lockdep_assert_held(&dev_priv->pps_mutex); in edp_have_panel_vdd()
636 struct drm_i915_private *dev_priv = dev->dev_private; in intel_dp_check_edp() local
654 struct drm_i915_private *dev_priv = dev->dev_private; in intel_dp_aux_wait_done() local
661 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, in intel_dp_aux_wait_done()
689 struct drm_i915_private *dev_priv = dev->dev_private; in ilk_get_aux_clock_divider() local
695 return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000); in ilk_get_aux_clock_divider()
706 struct drm_i915_private *dev_priv = dev->dev_private; in hsw_get_aux_clock_divider() local
711 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); in hsw_get_aux_clock_divider()
712 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { in hsw_get_aux_clock_divider()
791 struct drm_i915_private *dev_priv = dev->dev_private; in intel_dp_aux_ch() local
815 pm_qos_update_request(&dev_priv->pm_qos, 0); in intel_dp_aux_ch()
926 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); in intel_dp_aux_ch()
1012 struct drm_i915_private *dev_priv = dev->dev_private; in intel_dp_aux_init() local
1015 struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port]; in intel_dp_aux_init()
1383 struct drm_i915_private *dev_priv = dev->dev_private; in intel_dp_compute_config() local
1449 (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) { in intel_dp_compute_config()
1451 dev_priv->vbt.edp_bpp); in intel_dp_compute_config()
1452 bpp = dev_priv->vbt.edp_bpp; in intel_dp_compute_config()
1522 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { in intel_dp_compute_config()
1547 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_set_pll_cpu_edp() local
1583 struct drm_i915_private *dev_priv = dev->dev_private; in intel_dp_prepare() local
1679 struct drm_i915_private *dev_priv = dev->dev_private; in wait_panel_status() local
1682 lockdep_assert_held(&dev_priv->pps_mutex); in wait_panel_status()
1744 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_get_pp_control() local
1747 lockdep_assert_held(&dev_priv->pps_mutex); in ironlake_get_pp_control()
1767 struct drm_i915_private *dev_priv = dev->dev_private; in edp_panel_vdd_on() local
1773 lockdep_assert_held(&dev_priv->pps_mutex); in edp_panel_vdd_on()
1785 intel_display_power_get(dev_priv, power_domain); in edp_panel_vdd_on()
1840 struct drm_i915_private *dev_priv = dev->dev_private; in edp_panel_vdd_off_sync() local
1848 lockdep_assert_held(&dev_priv->pps_mutex); in edp_panel_vdd_off_sync()
1875 intel_display_power_put(dev_priv, power_domain); in edp_panel_vdd_off_sync()
1909 struct drm_i915_private *dev_priv = in edp_panel_vdd_off() local
1912 lockdep_assert_held(&dev_priv->pps_mutex); in edp_panel_vdd_off()
1931 struct drm_i915_private *dev_priv = dev->dev_private; in edp_panel_on() local
1935 lockdep_assert_held(&dev_priv->pps_mutex); in edp_panel_on()
1992 struct drm_i915_private *dev_priv = dev->dev_private; in edp_panel_off() local
1997 lockdep_assert_held(&dev_priv->pps_mutex); in edp_panel_off()
2026 intel_display_power_put(dev_priv, power_domain); in edp_panel_off()
2044 struct drm_i915_private *dev_priv = dev->dev_private; in _intel_edp_backlight_on() local
2085 struct drm_i915_private *dev_priv = dev->dev_private; in _intel_edp_backlight_off() local
2151 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_edp_pll_on() local
2154 assert_pipe_disabled(dev_priv, in ironlake_edp_pll_on()
2177 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_edp_pll_off() local
2180 assert_pipe_disabled(dev_priv, in ironlake_edp_pll_off()
2234 struct drm_i915_private *dev_priv = dev->dev_private; in intel_dp_get_hw_state() local
2239 if (!intel_display_power_is_enabled(dev_priv, power_domain)) in intel_dp_get_hw_state()
2252 for_each_pipe(dev_priv, p) { in intel_dp_get_hw_state()
2277 struct drm_i915_private *dev_priv = dev->dev_private; in intel_dp_get_config() local
2333 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) in intel_dp_get_config()
2338 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && in intel_dp_get_config()
2339 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { in intel_dp_get_config()
2354 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); in intel_dp_get_config()
2355 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; in intel_dp_get_config()
2403 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_data_lane_soft_reset() local
2409 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); in chv_data_lane_soft_reset()
2414 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); in chv_data_lane_soft_reset()
2417 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); in chv_data_lane_soft_reset()
2422 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); in chv_data_lane_soft_reset()
2425 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); in chv_data_lane_soft_reset()
2431 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); in chv_data_lane_soft_reset()
2434 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); in chv_data_lane_soft_reset()
2440 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); in chv_data_lane_soft_reset()
2448 struct drm_i915_private *dev_priv = dev->dev_private; in chv_post_disable_dp() local
2452 mutex_lock(&dev_priv->sb_lock); in chv_post_disable_dp()
2457 mutex_unlock(&dev_priv->sb_lock); in chv_post_disable_dp()
2467 struct drm_i915_private *dev_priv = dev->dev_private; in _intel_dp_set_link_train() local
2547 struct drm_i915_private *dev_priv = dev->dev_private; in intel_dp_enable_port() local
2572 struct drm_i915_private *dev_priv = dev->dev_private; in intel_enable_dp() local
2598 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), in intel_enable_dp()
2646 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private; in vlv_detach_power_sequencer() local
2672 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_steal_power_sequencer() local
2675 lockdep_assert_held(&dev_priv->pps_mutex); in vlv_steal_power_sequencer()
2711 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_init_panel_power_sequencer() local
2714 lockdep_assert_held(&dev_priv->pps_mutex); in vlv_init_panel_power_sequencer()
2752 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_pre_enable_dp() local
2758 mutex_lock(&dev_priv->sb_lock); in vlv_pre_enable_dp()
2760 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); in vlv_pre_enable_dp()
2767 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); in vlv_pre_enable_dp()
2768 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); in vlv_pre_enable_dp()
2769 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); in vlv_pre_enable_dp()
2771 mutex_unlock(&dev_priv->sb_lock); in vlv_pre_enable_dp()
2780 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_dp_pre_pll_enable() local
2789 mutex_lock(&dev_priv->sb_lock); in vlv_dp_pre_pll_enable()
2790 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), in vlv_dp_pre_pll_enable()
2793 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), in vlv_dp_pre_pll_enable()
2800 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); in vlv_dp_pre_pll_enable()
2801 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); in vlv_dp_pre_pll_enable()
2802 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); in vlv_dp_pre_pll_enable()
2803 mutex_unlock(&dev_priv->sb_lock); in vlv_dp_pre_pll_enable()
2811 struct drm_i915_private *dev_priv = dev->dev_private; in chv_pre_enable_dp() local
2819 mutex_lock(&dev_priv->sb_lock); in chv_pre_enable_dp()
2822 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); in chv_pre_enable_dp()
2824 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); in chv_pre_enable_dp()
2827 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); in chv_pre_enable_dp()
2829 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); in chv_pre_enable_dp()
2839 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), in chv_pre_enable_dp()
2855 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); in chv_pre_enable_dp()
2857 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); in chv_pre_enable_dp()
2860 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); in chv_pre_enable_dp()
2862 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); in chv_pre_enable_dp()
2865 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), in chv_pre_enable_dp()
2873 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), in chv_pre_enable_dp()
2884 mutex_unlock(&dev_priv->sb_lock); in chv_pre_enable_dp()
2890 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); in chv_pre_enable_dp()
2899 struct drm_i915_private *dev_priv = dev->dev_private; in chv_dp_pre_pll_enable() local
2916 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); in chv_dp_pre_pll_enable()
2920 mutex_lock(&dev_priv->sb_lock); in chv_dp_pre_pll_enable()
2927 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_dp_pre_pll_enable()
2933 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); in chv_dp_pre_pll_enable()
2935 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); in chv_dp_pre_pll_enable()
2941 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); in chv_dp_pre_pll_enable()
2945 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); in chv_dp_pre_pll_enable()
2951 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); in chv_dp_pre_pll_enable()
2954 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); in chv_dp_pre_pll_enable()
2960 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); in chv_dp_pre_pll_enable()
2968 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); in chv_dp_pre_pll_enable()
2973 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); in chv_dp_pre_pll_enable()
2975 mutex_unlock(&dev_priv->sb_lock); in chv_dp_pre_pll_enable()
2980 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_dp_post_pll_disable() local
2984 mutex_lock(&dev_priv->sb_lock); in chv_dp_post_pll_disable()
2988 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_dp_post_pll_disable()
2990 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); in chv_dp_post_pll_disable()
2992 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); in chv_dp_post_pll_disable()
2994 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); in chv_dp_post_pll_disable()
2997 mutex_unlock(&dev_priv->sb_lock); in chv_dp_post_pll_disable()
3060 struct drm_i915_private *dev_priv = dev->dev_private; in intel_dp_voltage_max() local
3066 if (dev_priv->edp_low_vswing && port == PORT_A) in intel_dp_voltage_max()
3150 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_signal_levels() local
3233 mutex_lock(&dev_priv->sb_lock); in vlv_signal_levels()
3234 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); in vlv_signal_levels()
3235 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); in vlv_signal_levels()
3236 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), in vlv_signal_levels()
3238 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); in vlv_signal_levels()
3239 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); in vlv_signal_levels()
3240 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); in vlv_signal_levels()
3241 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); in vlv_signal_levels()
3242 mutex_unlock(&dev_priv->sb_lock); in vlv_signal_levels()
3256 struct drm_i915_private *dev_priv = dev->dev_private; in chv_signal_levels() local
3335 mutex_lock(&dev_priv->sb_lock); in chv_signal_levels()
3338 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); in chv_signal_levels()
3342 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); in chv_signal_levels()
3345 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); in chv_signal_levels()
3349 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); in chv_signal_levels()
3352 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); in chv_signal_levels()
3355 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); in chv_signal_levels()
3358 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); in chv_signal_levels()
3361 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); in chv_signal_levels()
3366 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); in chv_signal_levels()
3369 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); in chv_signal_levels()
3374 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); in chv_signal_levels()
3387 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); in chv_signal_levels()
3397 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); in chv_signal_levels()
3402 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); in chv_signal_levels()
3406 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); in chv_signal_levels()
3408 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); in chv_signal_levels()
3411 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); in chv_signal_levels()
3413 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); in chv_signal_levels()
3416 mutex_unlock(&dev_priv->sb_lock); in chv_signal_levels()
3600 struct drm_i915_private *dev_priv = in intel_dp_set_link_train() local
3642 struct drm_i915_private *dev_priv = in intel_dp_update_link_train() local
3662 struct drm_i915_private *dev_priv = dev->dev_private; in intel_dp_set_idle_link_train() local
3922 struct drm_i915_private *dev_priv = dev->dev_private; in intel_dp_link_down() local
3976 struct drm_i915_private *dev_priv = dev->dev_private; in intel_dp_get_dpcd() local
3995 dev_priv->psr.sink_support = true; in intel_dp_get_dpcd()
4003 dev_priv->psr.sink_support = true; in intel_dp_get_dpcd()
4007 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; in intel_dp_get_dpcd()
4009 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; in intel_dp_get_dpcd()
4011 dev_priv->psr.psr2_support ? "supported" : "not supported"); in intel_dp_get_dpcd()
4540 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, in ibx_digital_port_connected() argument
4565 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, in cpt_digital_port_connected() argument
4593 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, in g4x_digital_port_connected() argument
4616 static bool vlv_digital_port_connected(struct drm_i915_private *dev_priv, in vlv_digital_port_connected() argument
4639 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, in bxt_digital_port_connected() argument
4672 bool intel_digital_port_connected(struct drm_i915_private *dev_priv, in intel_digital_port_connected() argument
4675 if (HAS_PCH_IBX(dev_priv)) in intel_digital_port_connected()
4676 return ibx_digital_port_connected(dev_priv, port); in intel_digital_port_connected()
4677 if (HAS_PCH_SPLIT(dev_priv)) in intel_digital_port_connected()
4678 return cpt_digital_port_connected(dev_priv, port); in intel_digital_port_connected()
4679 else if (IS_BROXTON(dev_priv)) in intel_digital_port_connected()
4680 return bxt_digital_port_connected(dev_priv, port); in intel_digital_port_connected()
4681 else if (IS_VALLEYVIEW(dev_priv)) in intel_digital_port_connected()
4682 return vlv_digital_port_connected(dev_priv, port); in intel_digital_port_connected()
4684 return g4x_digital_port_connected(dev_priv, port); in intel_digital_port_connected()
4691 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_dp_detect() local
4694 if (!intel_digital_port_connected(dev_priv, intel_dig_port)) in ironlake_dp_detect()
4843 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); in intel_dp_force() local
4854 intel_display_power_get(dev_priv, power_domain); in intel_dp_force()
4858 intel_display_power_put(dev_priv, power_domain); in intel_dp_force()
4910 struct drm_i915_private *dev_priv = connector->dev->dev_private; in intel_dp_set_property() local
4920 if (property == dev_priv->force_audio_property) { in intel_dp_set_property()
4941 if (property == dev_priv->broadcast_rgb_property) { in intel_dp_set_property()
5059 struct drm_i915_private *dev_priv = dev->dev_private; in intel_edp_panel_vdd_sanitize() local
5062 lockdep_assert_held(&dev_priv->pps_mutex); in intel_edp_panel_vdd_sanitize()
5075 intel_display_power_get(dev_priv, power_domain); in intel_edp_panel_vdd_sanitize()
5132 struct drm_i915_private *dev_priv = dev->dev_private; in intel_dp_hpd_pulse() local
5157 intel_display_power_get(dev_priv, power_domain); in intel_dp_hpd_pulse()
5163 if (!intel_digital_port_connected(dev_priv, intel_dig_port)) in intel_dp_hpd_pulse()
5202 intel_display_power_put(dev_priv, power_domain); in intel_dp_hpd_pulse()
5229 struct drm_i915_private *dev_priv = dev->dev_private; in intel_dp_is_edp() local
5249 if (!dev_priv->vbt.child_dev_num) in intel_dp_is_edp()
5252 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { in intel_dp_is_edp()
5253 p_child = dev_priv->vbt.child_dev + i; in intel_dp_is_edp()
5293 struct drm_i915_private *dev_priv = dev->dev_private; in intel_dp_init_panel_power_sequencer() local
5299 lockdep_assert_held(&dev_priv->pps_mutex); in intel_dp_init_panel_power_sequencer()
5367 vbt = dev_priv->vbt.edp_pps; in intel_dp_init_panel_power_sequencer()
5416 struct drm_i915_private *dev_priv = dev->dev_private; in intel_dp_init_panel_power_sequencer_registers() local
5423 lockdep_assert_held(&dev_priv->pps_mutex); in intel_dp_init_panel_power_sequencer_registers()
5514 struct drm_i915_private *dev_priv = dev->dev_private; in intel_dp_set_drrs_state() local
5517 struct intel_dp *intel_dp = dev_priv->drrs.dp; in intel_dp_set_drrs_state()
5548 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { in intel_dp_set_drrs_state()
5557 if (index == dev_priv->drrs.refresh_rate_type) { in intel_dp_set_drrs_state()
5599 dev_priv->drrs.refresh_rate_type = index; in intel_dp_set_drrs_state()
5613 struct drm_i915_private *dev_priv = dev->dev_private; in intel_edp_drrs_enable() local
5623 mutex_lock(&dev_priv->drrs.mutex); in intel_edp_drrs_enable()
5624 if (WARN_ON(dev_priv->drrs.dp)) { in intel_edp_drrs_enable()
5629 dev_priv->drrs.busy_frontbuffer_bits = 0; in intel_edp_drrs_enable()
5631 dev_priv->drrs.dp = intel_dp; in intel_edp_drrs_enable()
5634 mutex_unlock(&dev_priv->drrs.mutex); in intel_edp_drrs_enable()
5645 struct drm_i915_private *dev_priv = dev->dev_private; in intel_edp_drrs_disable() local
5653 mutex_lock(&dev_priv->drrs.mutex); in intel_edp_drrs_disable()
5654 if (!dev_priv->drrs.dp) { in intel_edp_drrs_disable()
5655 mutex_unlock(&dev_priv->drrs.mutex); in intel_edp_drrs_disable()
5659 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) in intel_edp_drrs_disable()
5660 intel_dp_set_drrs_state(dev_priv->dev, in intel_edp_drrs_disable()
5664 dev_priv->drrs.dp = NULL; in intel_edp_drrs_disable()
5665 mutex_unlock(&dev_priv->drrs.mutex); in intel_edp_drrs_disable()
5667 cancel_delayed_work_sync(&dev_priv->drrs.work); in intel_edp_drrs_disable()
5672 struct drm_i915_private *dev_priv = in intel_edp_drrs_downclock_work() local
5673 container_of(work, typeof(*dev_priv), drrs.work.work); in intel_edp_drrs_downclock_work()
5676 mutex_lock(&dev_priv->drrs.mutex); in intel_edp_drrs_downclock_work()
5678 intel_dp = dev_priv->drrs.dp; in intel_edp_drrs_downclock_work()
5688 if (dev_priv->drrs.busy_frontbuffer_bits) in intel_edp_drrs_downclock_work()
5691 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) in intel_edp_drrs_downclock_work()
5692 intel_dp_set_drrs_state(dev_priv->dev, in intel_edp_drrs_downclock_work()
5697 mutex_unlock(&dev_priv->drrs.mutex); in intel_edp_drrs_downclock_work()
5713 struct drm_i915_private *dev_priv = dev->dev_private; in intel_edp_drrs_invalidate() local
5717 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) in intel_edp_drrs_invalidate()
5720 cancel_delayed_work(&dev_priv->drrs.work); in intel_edp_drrs_invalidate()
5722 mutex_lock(&dev_priv->drrs.mutex); in intel_edp_drrs_invalidate()
5723 if (!dev_priv->drrs.dp) { in intel_edp_drrs_invalidate()
5724 mutex_unlock(&dev_priv->drrs.mutex); in intel_edp_drrs_invalidate()
5728 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; in intel_edp_drrs_invalidate()
5732 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; in intel_edp_drrs_invalidate()
5735 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) in intel_edp_drrs_invalidate()
5736 intel_dp_set_drrs_state(dev_priv->dev, in intel_edp_drrs_invalidate()
5737 dev_priv->drrs.dp->attached_connector->panel. in intel_edp_drrs_invalidate()
5740 mutex_unlock(&dev_priv->drrs.mutex); in intel_edp_drrs_invalidate()
5758 struct drm_i915_private *dev_priv = dev->dev_private; in intel_edp_drrs_flush() local
5762 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) in intel_edp_drrs_flush()
5765 cancel_delayed_work(&dev_priv->drrs.work); in intel_edp_drrs_flush()
5767 mutex_lock(&dev_priv->drrs.mutex); in intel_edp_drrs_flush()
5768 if (!dev_priv->drrs.dp) { in intel_edp_drrs_flush()
5769 mutex_unlock(&dev_priv->drrs.mutex); in intel_edp_drrs_flush()
5773 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; in intel_edp_drrs_flush()
5777 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; in intel_edp_drrs_flush()
5780 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) in intel_edp_drrs_flush()
5781 intel_dp_set_drrs_state(dev_priv->dev, in intel_edp_drrs_flush()
5782 dev_priv->drrs.dp->attached_connector->panel. in intel_edp_drrs_flush()
5789 if (!dev_priv->drrs.busy_frontbuffer_bits) in intel_edp_drrs_flush()
5790 schedule_delayed_work(&dev_priv->drrs.work, in intel_edp_drrs_flush()
5792 mutex_unlock(&dev_priv->drrs.mutex); in intel_edp_drrs_flush()
5851 struct drm_i915_private *dev_priv = dev->dev_private; in intel_dp_drrs_init() local
5854 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); in intel_dp_drrs_init()
5855 mutex_init(&dev_priv->drrs.mutex); in intel_dp_drrs_init()
5862 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { in intel_dp_drrs_init()
5875 dev_priv->drrs.type = dev_priv->vbt.drrs_type; in intel_dp_drrs_init()
5877 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; in intel_dp_drrs_init()
5889 struct drm_i915_private *dev_priv = dev->dev_private; in intel_edp_init_connector() local
5909 dev_priv->no_aux_handshake = in intel_edp_init_connector()
5950 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { in intel_edp_init_connector()
5952 dev_priv->vbt.lfp_lvds_vbt_mode); in intel_edp_init_connector()
5997 struct drm_i915_private *dev_priv = dev->dev_private; in intel_dp_init_connector() local
6071 if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) in intel_dp_init_connector()
6141 struct drm_i915_private *dev_priv = dev->dev_private; in intel_dp_init() local
6199 dev_priv->hotplug.irq_port[port] = intel_dig_port; in intel_dp_init()
6217 struct drm_i915_private *dev_priv = dev->dev_private; in intel_dp_mst_suspend() local
6222 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; in intel_dp_mst_suspend()
6237 struct drm_i915_private *dev_priv = dev->dev_private; in intel_dp_mst_resume() local
6241 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; in intel_dp_mst_resume()