520 	if (WARN_ON(!IS_VALLEYVIEW(dev)))  in vlv_power_sequencer_reset()
583 	if (IS_VALLEYVIEW(dev)) {  in edp_notify_handler()
611 	if (IS_VALLEYVIEW(dev) &&  in edp_have_panel_power()
625 	if (IS_VALLEYVIEW(dev) &&  in edp_have_panel_vdd()
1242 	} else if (IS_VALLEYVIEW(dev)) {  in intel_dp_set_clock()
1645 		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&  in intel_dp_prepare()
2312 	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&  in intel_dp_get_config()
2581 	if (IS_VALLEYVIEW(dev))  in intel_enable_dp()
2592 	if (IS_VALLEYVIEW(dev)) {  in intel_enable_dp()
3069 	} else if (IS_VALLEYVIEW(dev))  in intel_dp_voltage_max()
3110 	} else if (IS_VALLEYVIEW(dev)) {  in intel_dp_pre_emphasis_max()
3569 	} else if (IS_VALLEYVIEW(dev)) {  in intel_dp_set_signal_levels()
4681 	else if (IS_VALLEYVIEW(dev_priv))  in intel_digital_port_connected()
5095 	if (IS_VALLEYVIEW(encoder->dev))  in intel_dp_encoder_reset()
5474 	if (IS_VALLEYVIEW(dev)) {  in intel_dp_init_panel_power_sequencer_registers()
5586 			if (IS_VALLEYVIEW(dev))  in intel_dp_set_drrs_state()
5591 			if (IS_VALLEYVIEW(dev))  in intel_dp_set_drrs_state()
5958 	if (IS_VALLEYVIEW(dev)) {  in intel_edp_init_connector()
6006 	else if (IS_VALLEYVIEW(dev))  in intel_dp_init_connector()
6038 	if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&  in intel_dp_init_connector()
6090 		if (IS_VALLEYVIEW(dev))  in intel_dp_init_connector()
6172 	} else if (IS_VALLEYVIEW(dev)) {  in intel_dp_init()