310 	uint32_t DP;  in vlv_power_sequencer_kick()  local
323 	DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;  in vlv_power_sequencer_kick()
324 	DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;  in vlv_power_sequencer_kick()
325 	DP |= DP_PORT_WIDTH(1);  in vlv_power_sequencer_kick()
326 	DP |= DP_LINK_TRAIN_PAT_1;  in vlv_power_sequencer_kick()
329 		DP |= DP_PIPE_SELECT_CHV(pipe);  in vlv_power_sequencer_kick()
331 		DP |= DP_PIPEB_SELECT;  in vlv_power_sequencer_kick()
353 	I915_WRITE(intel_dp->output_reg, DP);  in vlv_power_sequencer_kick()
356 	I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);  in vlv_power_sequencer_kick()
359 	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);  in vlv_power_sequencer_kick()
1561 		intel_dp->DP |= DP_PLL_FREQ_160MHZ;  in ironlake_set_pll_cpu_edp()
1564 		intel_dp->DP |= DP_PLL_FREQ_270MHZ;  in ironlake_set_pll_cpu_edp()
1611 	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;  in intel_dp_prepare()
1614 	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;  in intel_dp_prepare()
1615 	intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);  in intel_dp_prepare()
1618 		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;  in intel_dp_prepare()
1624 			intel_dp->DP |= DP_SYNC_HS_HIGH;  in intel_dp_prepare()
1626 			intel_dp->DP |= DP_SYNC_VS_HIGH;  in intel_dp_prepare()
1627 		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;  in intel_dp_prepare()
1630 			intel_dp->DP |= DP_ENHANCED_FRAMING;  in intel_dp_prepare()
1632 		intel_dp->DP |= crtc->pipe << 29;  in intel_dp_prepare()
1636 		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;  in intel_dp_prepare()
1647 			intel_dp->DP |= DP_COLOR_RANGE_16_235;  in intel_dp_prepare()
1650 			intel_dp->DP |= DP_SYNC_HS_HIGH;  in intel_dp_prepare()
1652 			intel_dp->DP |= DP_SYNC_VS_HIGH;  in intel_dp_prepare()
1653 		intel_dp->DP |= DP_LINK_TRAIN_OFF;  in intel_dp_prepare()
1656 			intel_dp->DP |= DP_ENHANCED_FRAMING;  in intel_dp_prepare()
1659 			intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);  in intel_dp_prepare()
1661 			intel_dp->DP |= DP_PIPEB_SELECT;  in intel_dp_prepare()
2165 	intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);  in ironlake_edp_pll_on()
2166 	intel_dp->DP |= DP_PLL_ENABLE;  in ironlake_edp_pll_on()
2167 	I915_WRITE(DP_A, intel_dp->DP);  in ironlake_edp_pll_on()
2462 			 uint32_t *DP,  in _intel_dp_set_link_train()  argument
2498 		*DP &= ~DP_LINK_TRAIN_MASK_CPT;  in _intel_dp_set_link_train()
2502 			*DP |= DP_LINK_TRAIN_OFF_CPT;  in _intel_dp_set_link_train()
2505 			*DP |= DP_LINK_TRAIN_PAT_1_CPT;  in _intel_dp_set_link_train()
2508 			*DP |= DP_LINK_TRAIN_PAT_2_CPT;  in _intel_dp_set_link_train()
2512 			*DP |= DP_LINK_TRAIN_PAT_2_CPT;  in _intel_dp_set_link_train()
2518 			*DP &= ~DP_LINK_TRAIN_MASK_CHV;  in _intel_dp_set_link_train()
2520 			*DP &= ~DP_LINK_TRAIN_MASK;  in _intel_dp_set_link_train()
2524 			*DP |= DP_LINK_TRAIN_OFF;  in _intel_dp_set_link_train()
2527 			*DP |= DP_LINK_TRAIN_PAT_1;  in _intel_dp_set_link_train()
2530 			*DP |= DP_LINK_TRAIN_PAT_2;  in _intel_dp_set_link_train()
2534 				*DP |= DP_LINK_TRAIN_PAT_3_CHV;  in _intel_dp_set_link_train()
2537 				*DP |= DP_LINK_TRAIN_PAT_2;  in _intel_dp_set_link_train()
2550 	_intel_dp_set_link_train(intel_dp, &intel_dp->DP,  in intel_dp_enable_port()
2553 	I915_WRITE(intel_dp->output_reg, intel_dp->DP);  in intel_dp_enable_port()
2562 	intel_dp->DP |= DP_PORT_EN;  in intel_dp_enable_port()
2564 	I915_WRITE(intel_dp->output_reg, intel_dp->DP);  in intel_dp_enable_port()
3552 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)  in intel_dp_set_signal_levels()  argument
3591 	*DP = (*DP & ~mask) | signal_levels;  in intel_dp_set_signal_levels()
3596 			uint32_t *DP,  in intel_dp_set_link_train()  argument
3605 	_intel_dp_set_link_train(intel_dp, DP, dp_train_pat);  in intel_dp_set_link_train()
3607 	I915_WRITE(intel_dp->output_reg, *DP);  in intel_dp_set_link_train()
3628 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,  in intel_dp_reset_link_train()  argument
3633 	intel_dp_set_signal_levels(intel_dp, DP);  in intel_dp_reset_link_train()
3634 	return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);  in intel_dp_reset_link_train()
3638 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,  in intel_dp_update_link_train()  argument
3647 	intel_dp_set_signal_levels(intel_dp, DP);  in intel_dp_update_link_train()
3649 	I915_WRITE(intel_dp->output_reg, *DP);  in intel_dp_update_link_train()
3698 	uint32_t DP = intel_dp->DP;  in intel_dp_link_training_clock_recovery()  local
3722 	DP |= DP_PORT_EN;  in intel_dp_link_training_clock_recovery()
3725 	if (!intel_dp_reset_link_train(intel_dp, &DP,  in intel_dp_link_training_clock_recovery()
3757 			if (!intel_dp_reset_link_train(intel_dp, &DP,  in intel_dp_link_training_clock_recovery()
3776 			intel_dp_reset_link_train(intel_dp, &DP,  in intel_dp_link_training_clock_recovery()
3795 		if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {  in intel_dp_link_training_clock_recovery()
3801 	intel_dp->DP = DP;  in intel_dp_link_training_clock_recovery()
3811 	uint32_t DP = intel_dp->DP;  in intel_dp_link_training_channel_equalization()  local
3830 	if (!intel_dp_set_link_train(intel_dp, &DP,  in intel_dp_link_training_channel_equalization()
3859 			intel_dp_set_link_train(intel_dp, &DP,  in intel_dp_link_training_channel_equalization()
3876 			intel_dp_set_link_train(intel_dp, &DP,  in intel_dp_link_training_channel_equalization()
3885 		if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {  in intel_dp_link_training_channel_equalization()
3894 	intel_dp->DP = DP;  in intel_dp_link_training_channel_equalization()
3904 	intel_dp_set_link_train(intel_dp, &intel_dp->DP,  in intel_dp_stop_link_train()
3923 	uint32_t DP = intel_dp->DP;  in intel_dp_link_down()  local
3935 		DP &= ~DP_LINK_TRAIN_MASK_CPT;  in intel_dp_link_down()
3936 		DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;  in intel_dp_link_down()
3939 			DP &= ~DP_LINK_TRAIN_MASK_CHV;  in intel_dp_link_down()
3941 			DP &= ~DP_LINK_TRAIN_MASK;  in intel_dp_link_down()
3942 		DP |= DP_LINK_TRAIN_PAT_IDLE;  in intel_dp_link_down()
3944 	I915_WRITE(intel_dp->output_reg, DP);  in intel_dp_link_down()
3947 	DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);  in intel_dp_link_down()
3948 	I915_WRITE(intel_dp->output_reg, DP);  in intel_dp_link_down()
3958 		DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);  in intel_dp_link_down()
3959 		DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;  in intel_dp_link_down()
3960 		I915_WRITE(intel_dp->output_reg, DP);  in intel_dp_link_down()
3963 		DP &= ~DP_PORT_EN;  in intel_dp_link_down()
3964 		I915_WRITE(intel_dp->output_reg, DP);  in intel_dp_link_down()
5968 			pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);  in intel_edp_init_connector()
5970 			pipe = PORT_TO_PIPE(intel_dp->DP);  in intel_edp_init_connector()
6021 	intel_dp->DP = I915_READ(intel_dp->output_reg);  in intel_dp_init_connector()