1194 	if (crtc->config->shared_dpll < 0)  in intel_crtc_to_shared_dpll()
1197 	return &dev_priv->shared_dplls[crtc->config->shared_dpll];  in intel_crtc_to_shared_dpll()
4175 		if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)  in ironlake_pch_enable()
4255 	struct intel_shared_dpll_config *shared_dpll;  in intel_get_shared_dpll()  local
4259 	shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);  in intel_get_shared_dpll()
4269 		WARN_ON(shared_dpll[i].crtc_mask);  in intel_get_shared_dpll()
4289 		WARN_ON(shared_dpll[i].crtc_mask);  in intel_get_shared_dpll()
4300 		if (shared_dpll[i].crtc_mask == 0)  in intel_get_shared_dpll()
4304 			   &shared_dpll[i].hw_state,  in intel_get_shared_dpll()
4308 				      shared_dpll[i].crtc_mask,  in intel_get_shared_dpll()
4317 		if (shared_dpll[i].crtc_mask == 0) {  in intel_get_shared_dpll()
4327 	if (shared_dpll[i].crtc_mask == 0)  in intel_get_shared_dpll()
4328 		shared_dpll[i].hw_state =  in intel_get_shared_dpll()
4331 	crtc_state->shared_dpll = i;  in intel_get_shared_dpll()
4335 	shared_dpll[i].crtc_mask |= 1 << crtc->pipe;  in intel_get_shared_dpll()
4343 	struct intel_shared_dpll_config *shared_dpll;  in intel_shared_dpll_commit()  local
4350 	shared_dpll = to_intel_atomic_state(state)->shared_dpll;  in intel_shared_dpll_commit()
4353 		pll->config = shared_dpll[i];  in intel_shared_dpll_commit()
8141 	pipe_config->shared_dpll = DPLL_ID_PRIVATE;  in i9xx_get_pipe_config()
9272 	pipe_config->shared_dpll = DPLL_ID_PRIVATE;  in ironlake_get_pipe_config()
9310 			pipe_config->shared_dpll =  in ironlake_get_pipe_config()
9315 				pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;  in ironlake_get_pipe_config()
9317 				pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;  in ironlake_get_pipe_config()
9320 		pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];  in ironlake_get_pipe_config()
9739 		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;  in bxt_get_ddi_pll()
9743 		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;  in bxt_get_ddi_pll()
9747 		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;  in bxt_get_ddi_pll()
9774 		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;  in skylake_get_ddi_pll()
9777 		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;  in skylake_get_ddi_pll()
9780 		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;  in skylake_get_ddi_pll()
9793 		pipe_config->shared_dpll = DPLL_ID_WRPLL1;  in haswell_get_ddi_pll()
9796 		pipe_config->shared_dpll = DPLL_ID_WRPLL2;  in haswell_get_ddi_pll()
9799 		pipe_config->shared_dpll = DPLL_ID_SPLL;  in haswell_get_ddi_pll()
9823 	if (pipe_config->shared_dpll >= 0) {  in haswell_get_ddi_port_state()
9824 		pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];  in haswell_get_ddi_port_state()
9860 	pipe_config->shared_dpll = DPLL_ID_PRIVATE;  in haswell_get_pipe_config()
11870 	    !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {  in intel_crtc_atomic_check()
12188 	enum intel_dpll_id shared_dpll;  in clear_intel_crtc_state()  local
12199 	shared_dpll = crtc_state->shared_dpll;  in clear_intel_crtc_state()
12208 	crtc_state->shared_dpll = shared_dpll;  in clear_intel_crtc_state()
12608 	PIPE_CONF_CHECK_I(shared_dpll);  in intel_pipe_config_compare()
12935 	struct intel_shared_dpll_config *shared_dpll = NULL;  in intel_modeset_clear_plls()  local
12950 		dpll = intel_crtc_state->shared_dpll;  in intel_modeset_clear_plls()
12955 		intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;  in intel_modeset_clear_plls()
12957 		if (!shared_dpll)  in intel_modeset_clear_plls()
12958 			shared_dpll = intel_atomic_get_shared_dpll_state(state);  in intel_modeset_clear_plls()
12960 		shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);  in intel_modeset_clear_plls()