Lines Matching refs:plane
1371 enum plane plane, bool state) in assert_plane() argument
1376 val = I915_READ(DSPCNTR(plane)); in assert_plane()
1380 plane_name(plane), state_string(state), state_string(cur_state)); in assert_plane()
2220 uint64_t fb_format_modifier, unsigned int plane) in intel_tile_height() argument
2236 pixel_bytes = drm_format_plane_cpp(pixel_format, plane); in intel_tile_height()
2331 intel_pin_and_fence_fb_obj(struct drm_plane *plane, in intel_pin_and_fence_fb_obj() argument
2588 update_state_fb(struct drm_plane *plane) in update_state_fb() argument
2590 if (plane->fb == plane->state->fb) in update_state_fb()
2593 if (plane->state->fb) in update_state_fb()
2594 drm_framebuffer_unreference(plane->state->fb); in update_state_fb()
2595 plane->state->fb = plane->fb; in update_state_fb()
2596 if (plane->state->fb) in update_state_fb()
2597 drm_framebuffer_reference(plane->state->fb); in update_state_fb()
2695 int plane = intel_crtc->plane; in i9xx_update_primary_plane() local
2698 u32 reg = DSPCNTR(plane); in i9xx_update_primary_plane()
2704 I915_WRITE(DSPSURF(plane), 0); in i9xx_update_primary_plane()
2706 I915_WRITE(DSPADDR(plane), 0); in i9xx_update_primary_plane()
2728 I915_WRITE(DSPSIZE(plane), in i9xx_update_primary_plane()
2731 I915_WRITE(DSPPOS(plane), 0); in i9xx_update_primary_plane()
2732 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { in i9xx_update_primary_plane()
2733 I915_WRITE(PRIMSIZE(plane), in i9xx_update_primary_plane()
2736 I915_WRITE(PRIMPOS(plane), 0); in i9xx_update_primary_plane()
2737 I915_WRITE(PRIMCNSTALPHA(plane), 0); in i9xx_update_primary_plane()
2804 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); in i9xx_update_primary_plane()
2806 I915_WRITE(DSPSURF(plane), in i9xx_update_primary_plane()
2808 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); in i9xx_update_primary_plane()
2809 I915_WRITE(DSPLINOFF(plane), linear_offset); in i9xx_update_primary_plane()
2811 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); in i9xx_update_primary_plane()
2825 int plane = intel_crtc->plane; in ironlake_update_primary_plane() local
2828 u32 reg = DSPCNTR(plane); in ironlake_update_primary_plane()
2833 I915_WRITE(DSPSURF(plane), 0); in ironlake_update_primary_plane()
2907 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); in ironlake_update_primary_plane()
2908 I915_WRITE(DSPSURF(plane), in ironlake_update_primary_plane()
2911 I915_WRITE(DSPOFFSET(plane), (y << 16) | x); in ironlake_update_primary_plane()
2913 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); in ironlake_update_primary_plane()
2914 I915_WRITE(DSPLINOFF(plane), linear_offset); in ironlake_update_primary_plane()
2955 unsigned int plane) in intel_plane_obj_offset() argument
2971 if (plane == 1) { in intel_plane_obj_offset()
3094 struct drm_plane *plane = crtc->primary; in skylake_update_primary_plane() local
3095 bool visible = to_intel_plane_state(plane->state)->visible; in skylake_update_primary_plane()
3109 plane_state = to_intel_plane_state(plane->state); in skylake_update_primary_plane()
3126 rotation = plane->state->rotation; in skylake_update_primary_plane()
3132 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); in skylake_update_primary_plane()
3214 enum plane plane = intel_crtc->plane; in intel_complete_page_flips() local
3216 intel_prepare_page_flip(dev, plane); in intel_complete_page_flips()
3217 intel_finish_page_flip_plane(dev, plane); in intel_complete_page_flips()
3226 struct intel_plane *plane = to_intel_plane(crtc->primary); in intel_update_primary_planes() local
3229 drm_modeset_lock_crtc(crtc, &plane->base); in intel_update_primary_planes()
3231 plane_state = to_intel_plane_state(plane->base.state); in intel_update_primary_planes()
3234 plane->commit_plane(&plane->base, plane_state); in intel_update_primary_planes()
3951 trace_i915_flip_complete(intel_crtc->plane, in page_flip_completed()
4471 to_intel_plane(plane_state->base.plane); in skl_update_scaler_plane()
4591 assert_plane_enabled(dev_priv, crtc->plane); in hsw_enable_ips()
4621 assert_plane_enabled(dev_priv, crtc->plane); in hsw_disable_ips()
4810 struct drm_plane *plane; in intel_post_plane_update() local
4829 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks) in intel_post_plane_update()
4830 intel_update_sprite_watermarks(plane, &crtc->base, in intel_post_plane_update()
4845 struct intel_plane *plane = to_intel_plane(p); in intel_pre_plane_update() local
4848 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL, in intel_pre_plane_update()
4849 plane->frontbuffer_bit); in intel_pre_plane_update()
8037 int pipe = crtc->pipe, plane = crtc->plane; in i9xx_get_initial_plane_config() local
8043 val = I915_READ(DSPCNTR(plane)); in i9xx_get_initial_plane_config()
8069 offset = I915_READ(DSPTILEOFF(plane)); in i9xx_get_initial_plane_config()
8071 offset = I915_READ(DSPLINOFF(plane)); in i9xx_get_initial_plane_config()
8072 base = I915_READ(DSPSURF(plane)) & 0xfffff000; in i9xx_get_initial_plane_config()
8074 base = I915_READ(DSPADDR(plane)); in i9xx_get_initial_plane_config()
8092 pipe_name(pipe), plane, fb->width, fb->height, in i9xx_get_initial_plane_config()
10832 void intel_finish_page_flip_plane(struct drm_device *dev, int plane) in intel_finish_page_flip_plane() argument
10835 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; in intel_finish_page_flip_plane()
10880 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == in page_flip_finished()
10886 void intel_prepare_page_flip(struct drm_device *dev, int plane) in intel_prepare_page_flip() argument
10890 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); in intel_prepare_page_flip()
10936 if (intel_crtc->plane) in intel_gen2_queue_flip()
10943 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); in intel_gen2_queue_flip()
10968 if (intel_crtc->plane) in intel_gen3_queue_flip()
10975 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); in intel_gen3_queue_flip()
11006 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); in intel_gen4_queue_flip()
11041 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); in intel_gen6_queue_flip()
11071 switch (intel_crtc->plane) { in intel_gen7_queue_flip()
11238 reg = DSPCNTR(intel_crtc->plane); in ilk_do_mmio_flip()
11248 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); in ilk_do_mmio_flip()
11249 POSTING_READ(DSPSURF(intel_crtc->plane)); in ilk_do_mmio_flip()
11361 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); in __intel_pageflip_stall_check()
11363 addr = I915_READ(DSPADDR(intel_crtc->plane)); in __intel_pageflip_stall_check()
11565 trace_i915_flip_request(intel_crtc->plane, obj); in intel_crtc_page_flip()
11641 static bool intel_wm_need_update(struct drm_plane *plane, in intel_wm_need_update() argument
11645 if (!plane->state->fb || !state->fb || in intel_wm_need_update()
11646 plane->state->fb->modifier[0] != state->fb->modifier[0] || in intel_wm_need_update()
11647 plane->state->rotation != state->rotation) in intel_wm_need_update()
11650 if (plane->state->crtc_w != state->crtc_w) in intel_wm_need_update()
11661 struct drm_plane *plane = plane_state->plane; in intel_plane_atomic_calc_changes() local
11665 to_intel_plane_state(plane->state); in intel_plane_atomic_calc_changes()
11667 int i = drm_plane_index(plane); in intel_plane_atomic_calc_changes()
11676 plane->type != DRM_PLANE_TYPE_CURSOR) { in intel_plane_atomic_calc_changes()
11708 plane->base.id, fb ? fb->base.id : -1); in intel_plane_atomic_calc_changes()
11711 plane->base.id, was_visible, visible, in intel_plane_atomic_calc_changes()
11717 if (plane->type != DRM_PLANE_TYPE_CURSOR) { in intel_plane_atomic_calc_changes()
11726 if (plane->type != DRM_PLANE_TYPE_CURSOR) { in intel_plane_atomic_calc_changes()
11731 } else if (intel_wm_need_update(plane, plane_state)) { in intel_plane_atomic_calc_changes()
11737 to_intel_plane(plane)->frontbuffer_bit; in intel_plane_atomic_calc_changes()
11739 switch (plane->type) { in intel_plane_atomic_calc_changes()
12001 struct drm_plane *plane; in intel_dump_pipe_config() local
12099 list_for_each_entry(plane, &dev->mode_config.plane_list, head) { in intel_dump_pipe_config()
12100 intel_plane = to_intel_plane(plane); in intel_dump_pipe_config()
12104 state = to_intel_plane_state(plane->state); in intel_dump_pipe_config()
12109 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", in intel_dump_pipe_config()
12110 plane->base.id, intel_plane->pipe, in intel_dump_pipe_config()
12111 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, in intel_dump_pipe_config()
12112 drm_plane_index(plane), state->scaler_id); in intel_dump_pipe_config()
12117 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", in intel_dump_pipe_config()
12118 plane->base.id, intel_plane->pipe, in intel_dump_pipe_config()
12119 crtc->base.primary == plane ? 0 : intel_plane->plane + 1, in intel_dump_pipe_config()
12120 drm_plane_index(plane)); in intel_dump_pipe_config()
12641 int plane; in check_wm_state() local
12657 for_each_plane(dev_priv, pipe, plane) { in check_wm_state()
12658 hw_entry = &hw_ddb.plane[pipe][plane]; in check_wm_state()
12659 sw_entry = &sw_ddb->plane[pipe][plane]; in check_wm_state()
12666 pipe_name(pipe), plane + 1, in check_wm_state()
12672 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; in check_wm_state()
12673 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; in check_wm_state()
13451 intel_prepare_plane_fb(struct drm_plane *plane, in intel_prepare_plane_fb() argument
13454 struct drm_device *dev = plane->dev; in intel_prepare_plane_fb()
13456 struct intel_plane *intel_plane = to_intel_plane(plane); in intel_prepare_plane_fb()
13458 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); in intel_prepare_plane_fb()
13466 if (plane->type == DRM_PLANE_TYPE_CURSOR && in intel_prepare_plane_fb()
13473 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL); in intel_prepare_plane_fb()
13492 intel_cleanup_plane_fb(struct drm_plane *plane, in intel_cleanup_plane_fb() argument
13495 struct drm_device *dev = plane->dev; in intel_cleanup_plane_fb()
13501 if (plane->type != DRM_PLANE_TYPE_CURSOR || in intel_cleanup_plane_fb()
13540 intel_check_primary_plane(struct drm_plane *plane, in intel_check_primary_plane() argument
13550 if (INTEL_INFO(plane->dev)->gen >= 9) { in intel_check_primary_plane()
13559 return drm_plane_helper_check_update(plane, crtc, fb, &state->src, in intel_check_primary_plane()
13567 intel_commit_primary_plane(struct drm_plane *plane, in intel_commit_primary_plane() argument
13572 struct drm_device *dev = plane->dev; in intel_commit_primary_plane()
13577 crtc = crtc ? crtc : plane->crtc; in intel_commit_primary_plane()
13580 plane->fb = fb; in intel_commit_primary_plane()
13593 intel_disable_primary_plane(struct drm_plane *plane, in intel_disable_primary_plane() argument
13596 struct drm_device *dev = plane->dev; in intel_disable_primary_plane()
13643 void intel_plane_destroy(struct drm_plane *plane) in intel_plane_destroy() argument
13645 struct intel_plane *intel_plane = to_intel_plane(plane); in intel_plane_destroy()
13646 drm_plane_cleanup(plane); in intel_plane_destroy()
13688 primary->plane = pipe; in intel_primary_plane_create()
13694 primary->plane = !pipe; in intel_primary_plane_create()
13720 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) in intel_create_rotation_property() argument
13733 drm_object_attach_property(&plane->base.base, in intel_create_rotation_property()
13735 plane->base.state->rotation); in intel_create_rotation_property()
13739 intel_check_cursor_plane(struct drm_plane *plane, in intel_check_cursor_plane() argument
13746 enum pipe pipe = to_intel_plane(plane)->pipe; in intel_check_cursor_plane()
13750 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, in intel_check_cursor_plane()
13763 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { in intel_check_cursor_plane()
13790 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && in intel_check_cursor_plane()
13800 intel_disable_cursor_plane(struct drm_plane *plane, in intel_disable_cursor_plane() argument
13807 intel_commit_cursor_plane(struct drm_plane *plane, in intel_commit_cursor_plane() argument
13811 struct drm_device *dev = plane->dev; in intel_commit_cursor_plane()
13816 crtc = crtc ? crtc : plane->crtc; in intel_commit_cursor_plane()
13852 cursor->plane = pipe; in intel_cursor_plane_create()
13955 intel_crtc->plane = pipe; in intel_crtc_init()
13958 intel_crtc->plane = !pipe; in intel_crtc_init()
13968 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); in intel_crtc_init()
13969 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; in intel_crtc_init()
15033 val = I915_READ(DSPCNTR(!crtc->plane)); in intel_check_plane_mapping()
15066 struct intel_plane *plane; in intel_sanitize_crtc() local
15071 for_each_intel_plane_on_crtc(dev, crtc, plane) { in intel_sanitize_crtc()
15072 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) in intel_sanitize_crtc()
15075 plane->disable_plane(&plane->base, &crtc->base); in intel_sanitize_crtc()
15083 bool plane; in intel_sanitize_crtc() local
15091 plane = crtc->plane; in intel_sanitize_crtc()
15093 crtc->plane = !plane; in intel_sanitize_crtc()
15095 crtc->plane = plane; in intel_sanitize_crtc()
15239 static bool primary_get_hw_state(struct intel_plane *plane) in primary_get_hw_state() argument
15241 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in primary_get_hw_state()
15243 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; in primary_get_hw_state()
15435 struct intel_plane *plane; in intel_display_resume() local
15459 for_each_intel_plane(dev, plane) { in intel_display_resume()
15460 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base)); in intel_display_resume()
15656 } plane[I915_MAX_PIPES]; member
15707 error->plane[i].control = I915_READ(DSPCNTR(i)); in intel_display_capture_error_state()
15708 error->plane[i].stride = I915_READ(DSPSTRIDE(i)); in intel_display_capture_error_state()
15710 error->plane[i].size = I915_READ(DSPSIZE(i)); in intel_display_capture_error_state()
15711 error->plane[i].pos = I915_READ(DSPPOS(i)); in intel_display_capture_error_state()
15714 error->plane[i].addr = I915_READ(DSPADDR(i)); in intel_display_capture_error_state()
15716 error->plane[i].surface = I915_READ(DSPSURF(i)); in intel_display_capture_error_state()
15717 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); in intel_display_capture_error_state()
15778 err_printf(m, " CNTR: %08x\n", error->plane[i].control); in intel_display_print_error_state()
15779 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); in intel_display_print_error_state()
15781 err_printf(m, " SIZE: %08x\n", error->plane[i].size); in intel_display_print_error_state()
15782 err_printf(m, " POS: %08x\n", error->plane[i].pos); in intel_display_print_error_state()
15785 err_printf(m, " ADDR: %08x\n", error->plane[i].addr); in intel_display_print_error_state()
15787 err_printf(m, " SURF: %08x\n", error->plane[i].surface); in intel_display_print_error_state()
15788 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); in intel_display_print_error_state()