Lines Matching refs:pipe_src_w
2730 (intel_crtc->config->pipe_src_w - 1)); in i9xx_update_primary_plane()
2735 (intel_crtc->config->pipe_src_w - 1)); in i9xx_update_primary_plane()
2789 x += (intel_crtc->config->pipe_src_w - 1); in i9xx_update_primary_plane()
2796 (intel_crtc->config->pipe_src_w - 1) * pixel_size; in i9xx_update_primary_plane()
2891 x += (intel_crtc->config->pipe_src_w - 1); in ironlake_update_primary_plane()
2898 (intel_crtc->config->pipe_src_w - 1) * pixel_size; in ironlake_update_primary_plane()
3365 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, in intel_update_pipe_config()
3366 pipe_config->pipe_src_w, pipe_config->pipe_src_h); in intel_update_pipe_config()
3381 ((pipe_config->pipe_src_w - 1) << 16) | in intel_update_pipe_config()
4451 state->pipe_src_w, state->pipe_src_h, in skl_update_scaler_crtc()
6681 pipe_config->pipe_src_w &= ~1; in intel_crtc_compute_config()
7760 ((intel_crtc->config->pipe_src_w - 1) << 16) | in intel_set_pipe_timings()
7800 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7803 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; in intel_get_pipe_timings()
10051 if (x >= intel_crtc->config->pipe_src_w) in intel_crtc_update_cursor()
12045 pipe_config->pipe_src_w, pipe_config->pipe_src_h); in intel_dump_pipe_config()
12258 &pipe_config->pipe_src_w, in intel_modeset_pipe_config()
12588 PIPE_CONF_CHECK_I(pipe_src_w); in intel_pipe_config_compare()