Lines Matching refs:pipe_config
89 struct intel_crtc_state *pipe_config);
91 struct intel_crtc_state *pipe_config);
106 const struct intel_crtc_state *pipe_config);
108 const struct intel_crtc_state *pipe_config);
1599 const struct intel_crtc_state *pipe_config) in vlv_enable_pll() argument
1604 u32 dpll = pipe_config->dpll_hw_state.dpll; in vlv_enable_pll()
1622 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); in vlv_enable_pll()
1638 const struct intel_crtc_state *pipe_config) in chv_enable_pll() argument
1665 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in chv_enable_pll()
1672 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
3358 struct intel_crtc_state *pipe_config = in intel_update_pipe_config() local
3366 pipe_config->pipe_src_w, pipe_config->pipe_src_h); in intel_update_pipe_config()
3381 ((pipe_config->pipe_src_w - 1) << 16) | in intel_update_pipe_config()
3382 (pipe_config->pipe_src_h - 1)); in intel_update_pipe_config()
3388 if (pipe_config->pch_pfit.enabled) in intel_update_pipe_config()
3391 if (pipe_config->pch_pfit.enabled) in intel_update_pipe_config()
4973 struct intel_crtc_state *pipe_config = in haswell_crtc_enable() local
5055 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; in haswell_crtc_enable()
5178 struct intel_crtc_state *pipe_config = crtc->config; in i9xx_pfit_enable() local
5180 if (!pipe_config->gmch_pfit.control) in i9xx_pfit_enable()
5190 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); in i9xx_pfit_enable()
5191 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); in i9xx_pfit_enable()
6496 struct intel_crtc_state *pipe_config) in ironlake_check_fdi_lanes() argument
6498 struct drm_atomic_state *state = pipe_config->base.state; in ironlake_check_fdi_lanes()
6503 pipe_name(pipe), pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
6504 if (pipe_config->fdi_lanes > 4) { in ironlake_check_fdi_lanes()
6506 pipe_name(pipe), pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
6511 if (pipe_config->fdi_lanes > 2) { in ironlake_check_fdi_lanes()
6513 pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
6528 if (pipe_config->fdi_lanes <= 2) in ironlake_check_fdi_lanes()
6539 pipe_name(pipe), pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
6544 if (pipe_config->fdi_lanes > 2) { in ironlake_check_fdi_lanes()
6546 pipe_name(pipe), pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
6568 struct intel_crtc_state *pipe_config) in ironlake_fdi_compute_config() argument
6571 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in ironlake_fdi_compute_config()
6588 pipe_config->pipe_bpp); in ironlake_fdi_compute_config()
6590 pipe_config->fdi_lanes = lane; in ironlake_fdi_compute_config()
6592 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, in ironlake_fdi_compute_config()
6593 link_bw, &pipe_config->fdi_m_n); in ironlake_fdi_compute_config()
6596 intel_crtc->pipe, pipe_config); in ironlake_fdi_compute_config()
6597 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { in ironlake_fdi_compute_config()
6598 pipe_config->pipe_bpp -= 2*3; in ironlake_fdi_compute_config()
6600 pipe_config->pipe_bpp); in ironlake_fdi_compute_config()
6602 pipe_config->bw_constrained = true; in ironlake_fdi_compute_config()
6614 struct intel_crtc_state *pipe_config) in pipe_config_supports_ips() argument
6616 if (pipe_config->pipe_bpp > 24) in pipe_config_supports_ips()
6630 return ilk_pipe_pixel_rate(pipe_config) <= in pipe_config_supports_ips()
6635 struct intel_crtc_state *pipe_config) in hsw_compute_ips_config() argument
6640 pipe_config->ips_enabled = i915.enable_ips && in hsw_compute_ips_config()
6642 pipe_config_supports_ips(dev_priv, pipe_config); in hsw_compute_ips_config()
6646 struct intel_crtc_state *pipe_config) in intel_crtc_compute_config() argument
6650 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_crtc_compute_config()
6666 pipe_config->double_wide = true; in intel_crtc_compute_config()
6679 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && in intel_crtc_compute_config()
6680 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) in intel_crtc_compute_config()
6681 pipe_config->pipe_src_w &= ~1; in intel_crtc_compute_config()
6691 hsw_compute_ips_config(crtc, pipe_config); in intel_crtc_compute_config()
6693 if (pipe_config->has_pch_encoder) in intel_crtc_compute_config()
6694 return ironlake_fdi_compute_config(crtc, pipe_config); in intel_crtc_compute_config()
7303 struct intel_crtc_state *pipe_config) in vlv_compute_dpll() argument
7318 pipe_config->dpll_hw_state.dpll = dpll; in vlv_compute_dpll()
7320 dpll_md = (pipe_config->pixel_multiplier - 1) in vlv_compute_dpll()
7322 pipe_config->dpll_hw_state.dpll_md = dpll_md; in vlv_compute_dpll()
7326 const struct intel_crtc_state *pipe_config) in vlv_prepare_pll() argument
7337 bestn = pipe_config->dpll.n; in vlv_prepare_pll()
7338 bestm1 = pipe_config->dpll.m1; in vlv_prepare_pll()
7339 bestm2 = pipe_config->dpll.m2; in vlv_prepare_pll()
7340 bestp1 = pipe_config->dpll.p1; in vlv_prepare_pll()
7341 bestp2 = pipe_config->dpll.p2; in vlv_prepare_pll()
7378 if (pipe_config->port_clock == 162000 || in vlv_prepare_pll()
7387 if (pipe_config->has_dp_encoder) { in vlv_prepare_pll()
7417 struct intel_crtc_state *pipe_config) in chv_compute_dpll() argument
7419 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | in chv_compute_dpll()
7423 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in chv_compute_dpll()
7425 pipe_config->dpll_hw_state.dpll_md = in chv_compute_dpll()
7426 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; in chv_compute_dpll()
7430 const struct intel_crtc_state *pipe_config) in chv_prepare_pll() argument
7442 bestn = pipe_config->dpll.n; in chv_prepare_pll()
7443 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; in chv_prepare_pll()
7444 bestm1 = pipe_config->dpll.m1; in chv_prepare_pll()
7445 bestm2 = pipe_config->dpll.m2 >> 22; in chv_prepare_pll()
7446 bestp1 = pipe_config->dpll.p1; in chv_prepare_pll()
7447 bestp2 = pipe_config->dpll.p2; in chv_prepare_pll()
7448 vco = pipe_config->dpll.vco; in chv_prepare_pll()
7456 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); in chv_prepare_pll()
7548 struct intel_crtc_state pipe_config = { in vlv_force_pll_on() local
7555 chv_compute_dpll(crtc, &pipe_config); in vlv_force_pll_on()
7556 chv_prepare_pll(crtc, &pipe_config); in vlv_force_pll_on()
7557 chv_enable_pll(crtc, &pipe_config); in vlv_force_pll_on()
7559 vlv_compute_dpll(crtc, &pipe_config); in vlv_force_pll_on()
7560 vlv_prepare_pll(crtc, &pipe_config); in vlv_force_pll_on()
7561 vlv_enable_pll(crtc, &pipe_config); in vlv_force_pll_on()
7765 struct intel_crtc_state *pipe_config) in intel_get_pipe_timings() argument
7769 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_get_pipe_timings()
7773 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7774 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7776 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7777 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7779 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7780 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7783 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7784 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7786 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7787 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7789 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7790 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7793 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; in intel_get_pipe_timings()
7794 pipe_config->base.adjusted_mode.crtc_vtotal += 1; in intel_get_pipe_timings()
7795 pipe_config->base.adjusted_mode.crtc_vblank_end += 1; in intel_get_pipe_timings()
7799 pipe_config->pipe_src_h = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7800 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7802 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; in intel_get_pipe_timings()
7803 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; in intel_get_pipe_timings()
7807 struct intel_crtc_state *pipe_config) in intel_mode_from_pipe_config() argument
7809 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; in intel_mode_from_pipe_config()
7810 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; in intel_mode_from_pipe_config()
7811 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; in intel_mode_from_pipe_config()
7812 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; in intel_mode_from_pipe_config()
7814 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; in intel_mode_from_pipe_config()
7815 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; in intel_mode_from_pipe_config()
7816 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; in intel_mode_from_pipe_config()
7817 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; in intel_mode_from_pipe_config()
7819 mode->flags = pipe_config->base.adjusted_mode.flags; in intel_mode_from_pipe_config()
7822 mode->clock = pipe_config->base.adjusted_mode.crtc_clock; in intel_mode_from_pipe_config()
7823 mode->flags |= pipe_config->base.adjusted_mode.flags; in intel_mode_from_pipe_config()
7974 struct intel_crtc_state *pipe_config) in i9xx_get_pfit_config() argument
7996 pipe_config->gmch_pfit.control = tmp; in i9xx_get_pfit_config()
7997 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); in i9xx_get_pfit_config()
7999 pipe_config->gmch_pfit.lvds_border_bits = in i9xx_get_pfit_config()
8004 struct intel_crtc_state *pipe_config) in vlv_crtc_clock_get() argument
8008 int pipe = pipe_config->cpu_transcoder; in vlv_crtc_clock_get()
8014 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) in vlv_crtc_clock_get()
8027 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); in vlv_crtc_clock_get()
8100 struct intel_crtc_state *pipe_config) in chv_crtc_clock_get() argument
8104 int pipe = pipe_config->cpu_transcoder; in chv_crtc_clock_get()
8126 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); in chv_crtc_clock_get()
8130 struct intel_crtc_state *pipe_config) in i9xx_get_pipe_config() argument
8140 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in i9xx_get_pipe_config()
8141 pipe_config->shared_dpll = DPLL_ID_PRIVATE; in i9xx_get_pipe_config()
8150 pipe_config->pipe_bpp = 18; in i9xx_get_pipe_config()
8153 pipe_config->pipe_bpp = 24; in i9xx_get_pipe_config()
8156 pipe_config->pipe_bpp = 30; in i9xx_get_pipe_config()
8164 pipe_config->limited_color_range = true; in i9xx_get_pipe_config()
8167 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; in i9xx_get_pipe_config()
8169 intel_get_pipe_timings(crtc, pipe_config); in i9xx_get_pipe_config()
8171 i9xx_get_pfit_config(crtc, pipe_config); in i9xx_get_pipe_config()
8175 pipe_config->pixel_multiplier = in i9xx_get_pipe_config()
8178 pipe_config->dpll_hw_state.dpll_md = tmp; in i9xx_get_pipe_config()
8181 pipe_config->pixel_multiplier = in i9xx_get_pipe_config()
8188 pipe_config->pixel_multiplier = 1; in i9xx_get_pipe_config()
8190 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
8198 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; in i9xx_get_pipe_config()
8200 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); in i9xx_get_pipe_config()
8201 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); in i9xx_get_pipe_config()
8204 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | in i9xx_get_pipe_config()
8210 chv_crtc_clock_get(crtc, pipe_config); in i9xx_get_pipe_config()
8212 vlv_crtc_clock_get(crtc, pipe_config); in i9xx_get_pipe_config()
8214 i9xx_crtc_clock_get(crtc, pipe_config); in i9xx_get_pipe_config()
8221 pipe_config->base.adjusted_mode.crtc_clock = in i9xx_get_pipe_config()
8222 pipe_config->port_clock / pipe_config->pixel_multiplier; in i9xx_get_pipe_config()
9036 struct intel_crtc_state *pipe_config) in intel_dp_get_m_n() argument
9038 if (pipe_config->has_pch_encoder) in intel_dp_get_m_n()
9039 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); in intel_dp_get_m_n()
9041 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, in intel_dp_get_m_n()
9042 &pipe_config->dp_m_n, in intel_dp_get_m_n()
9043 &pipe_config->dp_m2_n2); in intel_dp_get_m_n()
9047 struct intel_crtc_state *pipe_config) in ironlake_get_fdi_m_n_config() argument
9049 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, in ironlake_get_fdi_m_n_config()
9050 &pipe_config->fdi_m_n, NULL); in ironlake_get_fdi_m_n_config()
9054 struct intel_crtc_state *pipe_config) in skylake_get_pfit_config() argument
9058 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; in skylake_get_pfit_config()
9068 pipe_config->pch_pfit.enabled = true; in skylake_get_pfit_config()
9069 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); in skylake_get_pfit_config()
9070 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); in skylake_get_pfit_config()
9168 struct intel_crtc_state *pipe_config) in ironlake_get_pfit_config() argument
9177 pipe_config->pch_pfit.enabled = true; in ironlake_get_pfit_config()
9178 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); in ironlake_get_pfit_config()
9179 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); in ironlake_get_pfit_config()
9261 struct intel_crtc_state *pipe_config) in ironlake_get_pipe_config() argument
9271 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in ironlake_get_pipe_config()
9272 pipe_config->shared_dpll = DPLL_ID_PRIVATE; in ironlake_get_pipe_config()
9280 pipe_config->pipe_bpp = 18; in ironlake_get_pipe_config()
9283 pipe_config->pipe_bpp = 24; in ironlake_get_pipe_config()
9286 pipe_config->pipe_bpp = 30; in ironlake_get_pipe_config()
9289 pipe_config->pipe_bpp = 36; in ironlake_get_pipe_config()
9296 pipe_config->limited_color_range = true; in ironlake_get_pipe_config()
9301 pipe_config->has_pch_encoder = true; in ironlake_get_pipe_config()
9304 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> in ironlake_get_pipe_config()
9307 ironlake_get_fdi_m_n_config(crtc, pipe_config); in ironlake_get_pipe_config()
9310 pipe_config->shared_dpll = in ironlake_get_pipe_config()
9315 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; in ironlake_get_pipe_config()
9317 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; in ironlake_get_pipe_config()
9320 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; in ironlake_get_pipe_config()
9323 &pipe_config->dpll_hw_state)); in ironlake_get_pipe_config()
9325 tmp = pipe_config->dpll_hw_state.dpll; in ironlake_get_pipe_config()
9326 pipe_config->pixel_multiplier = in ironlake_get_pipe_config()
9330 ironlake_pch_clock_get(crtc, pipe_config); in ironlake_get_pipe_config()
9332 pipe_config->pixel_multiplier = 1; in ironlake_get_pipe_config()
9335 intel_get_pipe_timings(crtc, pipe_config); in ironlake_get_pipe_config()
9337 ironlake_get_pfit_config(crtc, pipe_config); in ironlake_get_pipe_config()
9734 struct intel_crtc_state *pipe_config) in bxt_get_ddi_pll() argument
9738 pipe_config->ddi_pll_sel = SKL_DPLL0; in bxt_get_ddi_pll()
9739 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; in bxt_get_ddi_pll()
9742 pipe_config->ddi_pll_sel = SKL_DPLL1; in bxt_get_ddi_pll()
9743 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; in bxt_get_ddi_pll()
9746 pipe_config->ddi_pll_sel = SKL_DPLL2; in bxt_get_ddi_pll()
9747 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; in bxt_get_ddi_pll()
9756 struct intel_crtc_state *pipe_config) in skylake_get_ddi_pll() argument
9761 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); in skylake_get_ddi_pll()
9763 switch (pipe_config->ddi_pll_sel) { in skylake_get_ddi_pll()
9771 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; in skylake_get_ddi_pll()
9774 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; in skylake_get_ddi_pll()
9777 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; in skylake_get_ddi_pll()
9780 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; in skylake_get_ddi_pll()
9787 struct intel_crtc_state *pipe_config) in haswell_get_ddi_pll() argument
9789 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); in haswell_get_ddi_pll()
9791 switch (pipe_config->ddi_pll_sel) { in haswell_get_ddi_pll()
9793 pipe_config->shared_dpll = DPLL_ID_WRPLL1; in haswell_get_ddi_pll()
9796 pipe_config->shared_dpll = DPLL_ID_WRPLL2; in haswell_get_ddi_pll()
9799 pipe_config->shared_dpll = DPLL_ID_SPLL; in haswell_get_ddi_pll()
9804 struct intel_crtc_state *pipe_config) in haswell_get_ddi_port_state() argument
9812 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); in haswell_get_ddi_port_state()
9817 skylake_get_ddi_pll(dev_priv, port, pipe_config); in haswell_get_ddi_port_state()
9819 bxt_get_ddi_pll(dev_priv, port, pipe_config); in haswell_get_ddi_port_state()
9821 haswell_get_ddi_pll(dev_priv, port, pipe_config); in haswell_get_ddi_port_state()
9823 if (pipe_config->shared_dpll >= 0) { in haswell_get_ddi_port_state()
9824 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; in haswell_get_ddi_port_state()
9827 &pipe_config->dpll_hw_state)); in haswell_get_ddi_port_state()
9837 pipe_config->has_pch_encoder = true; in haswell_get_ddi_port_state()
9840 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> in haswell_get_ddi_port_state()
9843 ironlake_get_fdi_m_n_config(crtc, pipe_config); in haswell_get_ddi_port_state()
9848 struct intel_crtc_state *pipe_config) in haswell_get_pipe_config() argument
9859 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in haswell_get_pipe_config()
9860 pipe_config->shared_dpll = DPLL_ID_PRIVATE; in haswell_get_pipe_config()
9881 pipe_config->cpu_transcoder = TRANSCODER_EDP; in haswell_get_pipe_config()
9885 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) in haswell_get_pipe_config()
9888 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); in haswell_get_pipe_config()
9892 haswell_get_ddi_port_state(crtc, pipe_config); in haswell_get_pipe_config()
9894 intel_get_pipe_timings(crtc, pipe_config); in haswell_get_pipe_config()
9897 skl_init_scalers(dev, crtc, pipe_config); in haswell_get_pipe_config()
9903 pipe_config->scaler_state.scaler_id = -1; in haswell_get_pipe_config()
9904 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); in haswell_get_pipe_config()
9909 skylake_get_pfit_config(crtc, pipe_config); in haswell_get_pipe_config()
9911 ironlake_get_pfit_config(crtc, pipe_config); in haswell_get_pipe_config()
9915 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && in haswell_get_pipe_config()
9918 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { in haswell_get_pipe_config()
9919 pipe_config->pixel_multiplier = in haswell_get_pipe_config()
9920 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; in haswell_get_pipe_config()
9922 pipe_config->pixel_multiplier = 1; in haswell_get_pipe_config()
10527 const struct intel_crtc_state *pipe_config) in i9xx_pll_refclk() argument
10530 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_pll_refclk()
10544 struct intel_crtc_state *pipe_config) in i9xx_crtc_clock_get() argument
10548 int pipe = pipe_config->cpu_transcoder; in i9xx_crtc_clock_get()
10549 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_crtc_clock_get()
10553 int refclk = i9xx_pll_refclk(dev, pipe_config); in i9xx_crtc_clock_get()
10556 fp = pipe_config->dpll_hw_state.fp0; in i9xx_crtc_clock_get()
10558 fp = pipe_config->dpll_hw_state.fp1; in i9xx_crtc_clock_get()
10629 pipe_config->port_clock = port_clock; in i9xx_crtc_clock_get()
10652 struct intel_crtc_state *pipe_config) in ironlake_pch_clock_get() argument
10657 i9xx_crtc_clock_get(crtc, pipe_config); in ironlake_pch_clock_get()
10665 pipe_config->base.adjusted_mode.crtc_clock = in ironlake_pch_clock_get()
10667 &pipe_config->fdi_m_n); in ironlake_pch_clock_get()
10678 struct intel_crtc_state pipe_config; in intel_crtc_mode_get() local
10696 pipe_config.cpu_transcoder = (enum transcoder) pipe; in intel_crtc_mode_get()
10697 pipe_config.pixel_multiplier = 1; in intel_crtc_mode_get()
10698 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); in intel_crtc_mode_get()
10699 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); in intel_crtc_mode_get()
10700 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); in intel_crtc_mode_get()
10701 i9xx_crtc_clock_get(intel_crtc, &pipe_config); in intel_crtc_mode_get()
10703 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; in intel_crtc_mode_get()
11854 struct intel_crtc_state *pipe_config = in intel_crtc_atomic_check() local
11870 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) { in intel_crtc_atomic_check()
11872 pipe_config); in intel_crtc_atomic_check()
11880 ret = skl_update_scaler_crtc(pipe_config); in intel_crtc_atomic_check()
11884 pipe_config); in intel_crtc_atomic_check()
11917 struct intel_crtc_state *pipe_config) in connected_sink_compute_bpp() argument
11919 int bpp = pipe_config->pipe_bpp; in connected_sink_compute_bpp()
11930 pipe_config->pipe_bpp = connector->base.display_info.bpc*3; in connected_sink_compute_bpp()
11946 pipe_config->pipe_bpp = clamp_bpp; in connected_sink_compute_bpp()
11953 struct intel_crtc_state *pipe_config) in compute_baseline_pipe_bpp() argument
11969 pipe_config->pipe_bpp = bpp; in compute_baseline_pipe_bpp()
11971 state = pipe_config->base.state; in compute_baseline_pipe_bpp()
11979 pipe_config); in compute_baseline_pipe_bpp()
11997 struct intel_crtc_state *pipe_config, in intel_dump_pipe_config() argument
12007 context, pipe_config, pipe_name(crtc->pipe)); in intel_dump_pipe_config()
12009 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); in intel_dump_pipe_config()
12011 pipe_config->pipe_bpp, pipe_config->dither); in intel_dump_pipe_config()
12013 pipe_config->has_pch_encoder, in intel_dump_pipe_config()
12014 pipe_config->fdi_lanes, in intel_dump_pipe_config()
12015 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, in intel_dump_pipe_config()
12016 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, in intel_dump_pipe_config()
12017 pipe_config->fdi_m_n.tu); in intel_dump_pipe_config()
12019 pipe_config->has_dp_encoder, in intel_dump_pipe_config()
12020 pipe_config->lane_count, in intel_dump_pipe_config()
12021 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, in intel_dump_pipe_config()
12022 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, in intel_dump_pipe_config()
12023 pipe_config->dp_m_n.tu); in intel_dump_pipe_config()
12026 pipe_config->has_dp_encoder, in intel_dump_pipe_config()
12027 pipe_config->lane_count, in intel_dump_pipe_config()
12028 pipe_config->dp_m2_n2.gmch_m, in intel_dump_pipe_config()
12029 pipe_config->dp_m2_n2.gmch_n, in intel_dump_pipe_config()
12030 pipe_config->dp_m2_n2.link_m, in intel_dump_pipe_config()
12031 pipe_config->dp_m2_n2.link_n, in intel_dump_pipe_config()
12032 pipe_config->dp_m2_n2.tu); in intel_dump_pipe_config()
12035 pipe_config->has_audio, in intel_dump_pipe_config()
12036 pipe_config->has_infoframe); in intel_dump_pipe_config()
12039 drm_mode_debug_printmodeline(&pipe_config->base.mode); in intel_dump_pipe_config()
12041 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); in intel_dump_pipe_config()
12042 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); in intel_dump_pipe_config()
12043 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); in intel_dump_pipe_config()
12045 pipe_config->pipe_src_w, pipe_config->pipe_src_h); in intel_dump_pipe_config()
12048 pipe_config->scaler_state.scaler_users, in intel_dump_pipe_config()
12049 pipe_config->scaler_state.scaler_id); in intel_dump_pipe_config()
12051 pipe_config->gmch_pfit.control, in intel_dump_pipe_config()
12052 pipe_config->gmch_pfit.pgm_ratios, in intel_dump_pipe_config()
12053 pipe_config->gmch_pfit.lvds_border_bits); in intel_dump_pipe_config()
12055 pipe_config->pch_pfit.pos, in intel_dump_pipe_config()
12056 pipe_config->pch_pfit.size, in intel_dump_pipe_config()
12057 pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); in intel_dump_pipe_config()
12058 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); in intel_dump_pipe_config()
12059 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); in intel_dump_pipe_config()
12065 pipe_config->ddi_pll_sel, in intel_dump_pipe_config()
12066 pipe_config->dpll_hw_state.ebb0, in intel_dump_pipe_config()
12067 pipe_config->dpll_hw_state.ebb4, in intel_dump_pipe_config()
12068 pipe_config->dpll_hw_state.pll0, in intel_dump_pipe_config()
12069 pipe_config->dpll_hw_state.pll1, in intel_dump_pipe_config()
12070 pipe_config->dpll_hw_state.pll2, in intel_dump_pipe_config()
12071 pipe_config->dpll_hw_state.pll3, in intel_dump_pipe_config()
12072 pipe_config->dpll_hw_state.pll6, in intel_dump_pipe_config()
12073 pipe_config->dpll_hw_state.pll8, in intel_dump_pipe_config()
12074 pipe_config->dpll_hw_state.pll9, in intel_dump_pipe_config()
12075 pipe_config->dpll_hw_state.pll10, in intel_dump_pipe_config()
12076 pipe_config->dpll_hw_state.pcsdw12); in intel_dump_pipe_config()
12080 pipe_config->ddi_pll_sel, in intel_dump_pipe_config()
12081 pipe_config->dpll_hw_state.ctrl1, in intel_dump_pipe_config()
12082 pipe_config->dpll_hw_state.cfgcr1, in intel_dump_pipe_config()
12083 pipe_config->dpll_hw_state.cfgcr2); in intel_dump_pipe_config()
12086 pipe_config->ddi_pll_sel, in intel_dump_pipe_config()
12087 pipe_config->dpll_hw_state.wrpll, in intel_dump_pipe_config()
12088 pipe_config->dpll_hw_state.spll); in intel_dump_pipe_config()
12092 pipe_config->dpll_hw_state.dpll, in intel_dump_pipe_config()
12093 pipe_config->dpll_hw_state.dpll_md, in intel_dump_pipe_config()
12094 pipe_config->dpll_hw_state.fp0, in intel_dump_pipe_config()
12095 pipe_config->dpll_hw_state.fp1); in intel_dump_pipe_config()
12216 struct intel_crtc_state *pipe_config) in intel_modeset_pipe_config() argument
12218 struct drm_atomic_state *state = pipe_config->base.state; in intel_modeset_pipe_config()
12226 clear_intel_crtc_state(pipe_config); in intel_modeset_pipe_config()
12228 pipe_config->cpu_transcoder = in intel_modeset_pipe_config()
12236 if (!(pipe_config->base.adjusted_mode.flags & in intel_modeset_pipe_config()
12238 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; in intel_modeset_pipe_config()
12240 if (!(pipe_config->base.adjusted_mode.flags & in intel_modeset_pipe_config()
12242 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; in intel_modeset_pipe_config()
12245 pipe_config); in intel_modeset_pipe_config()
12257 drm_crtc_get_hv_timing(&pipe_config->base.mode, in intel_modeset_pipe_config()
12258 &pipe_config->pipe_src_w, in intel_modeset_pipe_config()
12259 &pipe_config->pipe_src_h); in intel_modeset_pipe_config()
12263 pipe_config->port_clock = 0; in intel_modeset_pipe_config()
12264 pipe_config->pixel_multiplier = 1; in intel_modeset_pipe_config()
12267 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, in intel_modeset_pipe_config()
12280 if (!(encoder->compute_config(encoder, pipe_config))) { in intel_modeset_pipe_config()
12288 if (!pipe_config->port_clock) in intel_modeset_pipe_config()
12289 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock in intel_modeset_pipe_config()
12290 * pipe_config->pixel_multiplier; in intel_modeset_pipe_config()
12292 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); in intel_modeset_pipe_config()
12311 pipe_config->dither = pipe_config->pipe_bpp == 6*3; in intel_modeset_pipe_config()
12313 base_bpp, pipe_config->pipe_bpp, pipe_config->dither); in intel_modeset_pipe_config()
12412 struct intel_crtc_state *pipe_config, in intel_pipe_config_compare() argument
12426 if (current_config->name != pipe_config->name) { \ in intel_pipe_config_compare()
12430 pipe_config->name); \ in intel_pipe_config_compare()
12435 if (current_config->name != pipe_config->name) { \ in intel_pipe_config_compare()
12439 pipe_config->name); \ in intel_pipe_config_compare()
12445 &pipe_config->name,\ in intel_pipe_config_compare()
12455 pipe_config->name.tu, \ in intel_pipe_config_compare()
12456 pipe_config->name.gmch_m, \ in intel_pipe_config_compare()
12457 pipe_config->name.gmch_n, \ in intel_pipe_config_compare()
12458 pipe_config->name.link_m, \ in intel_pipe_config_compare()
12459 pipe_config->name.link_n); \ in intel_pipe_config_compare()
12465 &pipe_config->name, adjust) && \ in intel_pipe_config_compare()
12467 &pipe_config->name, adjust)) { \ in intel_pipe_config_compare()
12482 pipe_config->name.tu, \ in intel_pipe_config_compare()
12483 pipe_config->name.gmch_m, \ in intel_pipe_config_compare()
12484 pipe_config->name.gmch_n, \ in intel_pipe_config_compare()
12485 pipe_config->name.link_m, \ in intel_pipe_config_compare()
12486 pipe_config->name.link_n); \ in intel_pipe_config_compare()
12496 if ((current_config->name != pipe_config->name) && \ in intel_pipe_config_compare()
12497 (current_config->alt_name != pipe_config->name)) { \ in intel_pipe_config_compare()
12502 pipe_config->name); \ in intel_pipe_config_compare()
12507 if ((current_config->name ^ pipe_config->name) & (mask)) { \ in intel_pipe_config_compare()
12511 pipe_config->name & (mask)); \ in intel_pipe_config_compare()
12516 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ in intel_pipe_config_compare()
12520 pipe_config->name); \ in intel_pipe_config_compare()
12525 ((current_config->quirks | pipe_config->quirks) & (quirk)) in intel_pipe_config_compare()
12758 struct intel_crtc_state *pipe_config, *sw_config; in check_crtc_state() local
12766 pipe_config = to_intel_crtc_state(old_crtc_state); in check_crtc_state()
12767 memset(pipe_config, 0, sizeof(*pipe_config)); in check_crtc_state()
12768 pipe_config->base.crtc = crtc; in check_crtc_state()
12769 pipe_config->base.state = old_state; in check_crtc_state()
12775 pipe_config); in check_crtc_state()
12803 encoder->get_config(encoder, pipe_config); in check_crtc_state()
12811 pipe_config, false)) { in check_crtc_state()
12813 intel_dump_pipe_config(intel_crtc, pipe_config, in check_crtc_state()
12881 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, in ironlake_check_encoder_dotclock() argument
12888 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), in ironlake_check_encoder_dotclock()
12890 pipe_config->base.adjusted_mode.crtc_clock, dotclock); in ironlake_check_encoder_dotclock()
13002 struct intel_crtc_state *pipe_config; in haswell_mode_set_planes_workaround() local
13004 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); in haswell_mode_set_planes_workaround()
13005 if (IS_ERR(pipe_config)) in haswell_mode_set_planes_workaround()
13006 return PTR_ERR(pipe_config); in haswell_mode_set_planes_workaround()
13008 pipe_config->hsw_workaround_pipe = INVALID_PIPE; in haswell_mode_set_planes_workaround()
13010 if (!pipe_config->base.active || in haswell_mode_set_planes_workaround()
13011 needs_modeset(&pipe_config->base)) in haswell_mode_set_planes_workaround()
13116 struct intel_crtc_state *pipe_config = in intel_atomic_check() local
13142 ret = intel_modeset_pipe_config(crtc, pipe_config); in intel_atomic_check()
13149 pipe_config, true)) { in intel_atomic_check()
13162 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, in intel_atomic_check()