Lines Matching refs:pipe
1088 enum pipe pipe) in intel_pipe_to_cpu_transcoder() argument
1090 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in intel_pipe_to_cpu_transcoder()
1096 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) in pipe_dsl_stopped() argument
1099 u32 reg = PIPEDSL(pipe); in pipe_dsl_stopped()
1136 enum pipe pipe = crtc->pipe; in intel_wait_for_pipe_off() local
1147 if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) in intel_wait_for_pipe_off()
1159 enum pipe pipe, bool state) in assert_pll() argument
1164 val = I915_READ(DPLL(pipe)); in assert_pll()
1219 enum pipe pipe, bool state) in assert_fdi_tx() argument
1223 pipe); in assert_fdi_tx()
1230 u32 val = I915_READ(FDI_TX_CTL(pipe)); in assert_fdi_tx()
1241 enum pipe pipe, bool state) in assert_fdi_rx() argument
1246 val = I915_READ(FDI_RX_CTL(pipe)); in assert_fdi_rx()
1256 enum pipe pipe) in assert_fdi_tx_pll_enabled() argument
1268 val = I915_READ(FDI_TX_CTL(pipe)); in assert_fdi_tx_pll_enabled()
1273 enum pipe pipe, bool state) in assert_fdi_rx_pll() argument
1278 val = I915_READ(FDI_RX_CTL(pipe)); in assert_fdi_rx_pll()
1286 enum pipe pipe) in assert_panel_unlocked() argument
1291 enum pipe panel_pipe = PIPE_A; in assert_panel_unlocked()
1309 pp_reg = VLV_PIPE_PP_CONTROL(pipe); in assert_panel_unlocked()
1310 panel_pipe = pipe; in assert_panel_unlocked()
1322 I915_STATE_WARN(panel_pipe == pipe && locked, in assert_panel_unlocked()
1324 pipe_name(pipe)); in assert_panel_unlocked()
1328 enum pipe pipe, bool state) in assert_cursor() argument
1336 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; in assert_cursor()
1340 pipe_name(pipe), state_string(state), state_string(cur_state)); in assert_cursor()
1346 enum pipe pipe, bool state) in assert_pipe() argument
1350 pipe); in assert_pipe()
1353 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in assert_pipe()
1354 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in assert_pipe()
1367 pipe_name(pipe), state_string(state), state_string(cur_state)); in assert_pipe()
1387 enum pipe pipe) in assert_planes_disabled() argument
1394 u32 val = I915_READ(DSPCNTR(pipe)); in assert_planes_disabled()
1397 plane_name(pipe)); in assert_planes_disabled()
1404 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> in assert_planes_disabled()
1406 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, in assert_planes_disabled()
1408 plane_name(i), pipe_name(pipe)); in assert_planes_disabled()
1413 enum pipe pipe) in assert_sprites_disabled() argument
1419 for_each_sprite(dev_priv, pipe, sprite) { in assert_sprites_disabled()
1420 u32 val = I915_READ(PLANE_CTL(pipe, sprite)); in assert_sprites_disabled()
1423 sprite, pipe_name(pipe)); in assert_sprites_disabled()
1426 for_each_sprite(dev_priv, pipe, sprite) { in assert_sprites_disabled()
1427 u32 val = I915_READ(SPCNTR(pipe, sprite)); in assert_sprites_disabled()
1430 sprite_name(pipe, sprite), pipe_name(pipe)); in assert_sprites_disabled()
1433 u32 val = I915_READ(SPRCTL(pipe)); in assert_sprites_disabled()
1436 plane_name(pipe), pipe_name(pipe)); in assert_sprites_disabled()
1438 u32 val = I915_READ(DVSCNTR(pipe)); in assert_sprites_disabled()
1441 plane_name(pipe), pipe_name(pipe)); in assert_sprites_disabled()
1465 enum pipe pipe) in assert_pch_transcoder_disabled() argument
1470 val = I915_READ(PCH_TRANSCONF(pipe)); in assert_pch_transcoder_disabled()
1474 pipe_name(pipe)); in assert_pch_transcoder_disabled()
1478 enum pipe pipe, u32 port_sel, u32 val) in dp_pipe_enabled() argument
1484 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); in dp_pipe_enabled()
1489 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) in dp_pipe_enabled()
1492 if ((val & DP_PIPE_MASK) != (pipe << 30)) in dp_pipe_enabled()
1499 enum pipe pipe, u32 val) in hdmi_pipe_enabled() argument
1505 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) in hdmi_pipe_enabled()
1508 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) in hdmi_pipe_enabled()
1511 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) in hdmi_pipe_enabled()
1518 enum pipe pipe, u32 val) in lvds_pipe_enabled() argument
1524 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) in lvds_pipe_enabled()
1527 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) in lvds_pipe_enabled()
1534 enum pipe pipe, u32 val) in adpa_pipe_enabled() argument
1539 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) in adpa_pipe_enabled()
1542 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) in adpa_pipe_enabled()
1549 enum pipe pipe, int reg, u32 port_sel) in assert_pch_dp_disabled() argument
1552 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), in assert_pch_dp_disabled()
1554 reg, pipe_name(pipe)); in assert_pch_dp_disabled()
1562 enum pipe pipe, int reg) in assert_pch_hdmi_disabled() argument
1565 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), in assert_pch_hdmi_disabled()
1567 reg, pipe_name(pipe)); in assert_pch_hdmi_disabled()
1575 enum pipe pipe) in assert_pch_ports_disabled() argument
1579 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); in assert_pch_ports_disabled()
1580 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); in assert_pch_ports_disabled()
1581 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); in assert_pch_ports_disabled()
1584 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), in assert_pch_ports_disabled()
1586 pipe_name(pipe)); in assert_pch_ports_disabled()
1589 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), in assert_pch_ports_disabled()
1591 pipe_name(pipe)); in assert_pch_ports_disabled()
1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); in assert_pch_ports_disabled()
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); in assert_pch_ports_disabled()
1595 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); in assert_pch_ports_disabled()
1603 int reg = DPLL(crtc->pipe); in vlv_enable_pll()
1606 assert_pipe_disabled(dev_priv, crtc->pipe); in vlv_enable_pll()
1613 assert_panel_unlocked(dev_priv, crtc->pipe); in vlv_enable_pll()
1620 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); in vlv_enable_pll()
1622 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); in vlv_enable_pll()
1623 POSTING_READ(DPLL_MD(crtc->pipe)); in vlv_enable_pll()
1642 int pipe = crtc->pipe; in chv_enable_pll() local
1643 enum dpio_channel port = vlv_pipe_to_channel(pipe); in chv_enable_pll()
1646 assert_pipe_disabled(dev_priv, crtc->pipe); in chv_enable_pll()
1653 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); in chv_enable_pll()
1655 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); in chv_enable_pll()
1665 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in chv_enable_pll()
1668 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) in chv_enable_pll()
1669 DRM_ERROR("PLL %d failed to lock\n", pipe); in chv_enable_pll()
1672 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
1673 POSTING_READ(DPLL_MD(pipe)); in chv_enable_pll()
1692 int reg = DPLL(crtc->pipe); in i9xx_enable_pll()
1695 assert_pipe_disabled(dev_priv, crtc->pipe); in i9xx_enable_pll()
1702 assert_panel_unlocked(dev_priv, crtc->pipe); in i9xx_enable_pll()
1713 I915_WRITE(DPLL(!crtc->pipe), in i9xx_enable_pll()
1714 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); in i9xx_enable_pll()
1731 I915_WRITE(DPLL_MD(crtc->pipe), in i9xx_enable_pll()
1767 enum pipe pipe = crtc->pipe; in i9xx_disable_pll() local
1780 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in i9xx_disable_pll()
1781 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in i9xx_disable_pll()
1785 assert_pipe_disabled(dev_priv, pipe); in i9xx_disable_pll()
1787 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); in i9xx_disable_pll()
1788 POSTING_READ(DPLL(pipe)); in i9xx_disable_pll()
1791 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) in vlv_disable_pll() argument
1796 assert_pipe_disabled(dev_priv, pipe); in vlv_disable_pll()
1803 if (pipe == PIPE_B) in vlv_disable_pll()
1805 I915_WRITE(DPLL(pipe), val); in vlv_disable_pll()
1806 POSTING_READ(DPLL(pipe)); in vlv_disable_pll()
1810 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) in chv_disable_pll() argument
1812 enum dpio_channel port = vlv_pipe_to_channel(pipe); in chv_disable_pll()
1816 assert_pipe_disabled(dev_priv, pipe); in chv_disable_pll()
1821 if (pipe != PIPE_A) in chv_disable_pll()
1823 I915_WRITE(DPLL(pipe), val); in chv_disable_pll()
1824 POSTING_READ(DPLL(pipe)); in chv_disable_pll()
1829 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); in chv_disable_pll()
1831 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); in chv_disable_pll()
1961 enum pipe pipe) in ironlake_enable_pch_transcoder() argument
1964 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in ironlake_enable_pch_transcoder()
1976 assert_fdi_tx_enabled(dev_priv, pipe); in ironlake_enable_pch_transcoder()
1977 assert_fdi_rx_enabled(dev_priv, pipe); in ironlake_enable_pch_transcoder()
1982 reg = TRANS_CHICKEN2(pipe); in ironlake_enable_pch_transcoder()
1988 reg = PCH_TRANSCONF(pipe); in ironlake_enable_pch_transcoder()
1990 pipeconf_val = I915_READ(PIPECONF(pipe)); in ironlake_enable_pch_transcoder()
2017 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); in ironlake_enable_pch_transcoder()
2029 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); in lpt_enable_pch_transcoder()
2052 enum pipe pipe) in ironlake_disable_pch_transcoder() argument
2058 assert_fdi_tx_disabled(dev_priv, pipe); in ironlake_disable_pch_transcoder()
2059 assert_fdi_rx_disabled(dev_priv, pipe); in ironlake_disable_pch_transcoder()
2062 assert_pch_ports_disabled(dev_priv, pipe); in ironlake_disable_pch_transcoder()
2064 reg = PCH_TRANSCONF(pipe); in ironlake_disable_pch_transcoder()
2070 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); in ironlake_disable_pch_transcoder()
2074 reg = TRANS_CHICKEN2(pipe); in ironlake_disable_pch_transcoder()
2109 enum pipe pipe = crtc->pipe; in intel_enable_pipe() local
2111 pipe); in intel_enable_pipe()
2112 enum pipe pch_transcoder; in intel_enable_pipe()
2116 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); in intel_enable_pipe()
2118 assert_planes_disabled(dev_priv, pipe); in intel_enable_pipe()
2119 assert_cursor_disabled(dev_priv, pipe); in intel_enable_pipe()
2120 assert_sprites_disabled(dev_priv, pipe); in intel_enable_pipe()
2125 pch_transcoder = pipe; in intel_enable_pipe()
2136 assert_pll_enabled(dev_priv, pipe); in intel_enable_pipe()
2142 (enum pipe) cpu_transcoder); in intel_enable_pipe()
2150 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in intel_enable_pipe()
2151 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); in intel_enable_pipe()
2173 enum pipe pipe = crtc->pipe; in intel_disable_pipe() local
2177 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); in intel_disable_pipe()
2183 assert_planes_disabled(dev_priv, pipe); in intel_disable_pipe()
2184 assert_cursor_disabled(dev_priv, pipe); in intel_disable_pipe()
2185 assert_sprites_disabled(dev_priv, pipe); in intel_disable_pipe()
2200 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && in intel_disable_pipe()
2201 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in intel_disable_pipe()
2722 if (intel_crtc->pipe == PIPE_B) in i9xx_update_primary_plane()
2984 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); in skl_detach_scaler()
2985 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); in skl_detach_scaler()
2986 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); in skl_detach_scaler()
3097 int pipe = intel_crtc->pipe; in skylake_update_primary_plane() local
3112 I915_WRITE(PLANE_CTL(pipe, 0), 0); in skylake_update_primary_plane()
3113 I915_WRITE(PLANE_SURF(pipe, 0), 0); in skylake_update_primary_plane()
3114 POSTING_READ(PLANE_CTL(pipe, 0)); in skylake_update_primary_plane()
3167 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); in skylake_update_primary_plane()
3168 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); in skylake_update_primary_plane()
3169 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); in skylake_update_primary_plane()
3170 I915_WRITE(PLANE_STRIDE(pipe, 0), stride); in skylake_update_primary_plane()
3178 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); in skylake_update_primary_plane()
3179 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); in skylake_update_primary_plane()
3180 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); in skylake_update_primary_plane()
3181 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); in skylake_update_primary_plane()
3182 I915_WRITE(PLANE_POS(pipe, 0), 0); in skylake_update_primary_plane()
3184 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); in skylake_update_primary_plane()
3187 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); in skylake_update_primary_plane()
3189 POSTING_READ(PLANE_SURF(pipe, 0)); in skylake_update_primary_plane()
3380 I915_WRITE(PIPESRC(crtc->pipe), in intel_update_pipe_config()
3403 int pipe = intel_crtc->pipe; in intel_fdi_normal_train() local
3407 reg = FDI_TX_CTL(pipe); in intel_fdi_normal_train()
3418 reg = FDI_RX_CTL(pipe); in intel_fdi_normal_train()
3445 int pipe = intel_crtc->pipe; in ironlake_fdi_link_train() local
3449 assert_pipe_enabled(dev_priv, pipe); in ironlake_fdi_link_train()
3453 reg = FDI_RX_IMR(pipe); in ironlake_fdi_link_train()
3462 reg = FDI_TX_CTL(pipe); in ironlake_fdi_link_train()
3470 reg = FDI_RX_CTL(pipe); in ironlake_fdi_link_train()
3480 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); in ironlake_fdi_link_train()
3481 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | in ironlake_fdi_link_train()
3484 reg = FDI_RX_IIR(pipe); in ironlake_fdi_link_train()
3499 reg = FDI_TX_CTL(pipe); in ironlake_fdi_link_train()
3505 reg = FDI_RX_CTL(pipe); in ironlake_fdi_link_train()
3514 reg = FDI_RX_IIR(pipe); in ironlake_fdi_link_train()
3545 int pipe = intel_crtc->pipe; in gen6_fdi_link_train() local
3550 reg = FDI_RX_IMR(pipe); in gen6_fdi_link_train()
3560 reg = FDI_TX_CTL(pipe); in gen6_fdi_link_train()
3571 I915_WRITE(FDI_RX_MISC(pipe), in gen6_fdi_link_train()
3574 reg = FDI_RX_CTL(pipe); in gen6_fdi_link_train()
3589 reg = FDI_TX_CTL(pipe); in gen6_fdi_link_train()
3599 reg = FDI_RX_IIR(pipe); in gen6_fdi_link_train()
3616 reg = FDI_TX_CTL(pipe); in gen6_fdi_link_train()
3627 reg = FDI_RX_CTL(pipe); in gen6_fdi_link_train()
3642 reg = FDI_TX_CTL(pipe); in gen6_fdi_link_train()
3652 reg = FDI_RX_IIR(pipe); in gen6_fdi_link_train()
3677 int pipe = intel_crtc->pipe; in ivb_manual_fdi_link_train() local
3682 reg = FDI_RX_IMR(pipe); in ivb_manual_fdi_link_train()
3692 I915_READ(FDI_RX_IIR(pipe))); in ivb_manual_fdi_link_train()
3697 reg = FDI_TX_CTL(pipe); in ivb_manual_fdi_link_train()
3703 reg = FDI_RX_CTL(pipe); in ivb_manual_fdi_link_train()
3711 reg = FDI_TX_CTL(pipe); in ivb_manual_fdi_link_train()
3721 I915_WRITE(FDI_RX_MISC(pipe), in ivb_manual_fdi_link_train()
3724 reg = FDI_RX_CTL(pipe); in ivb_manual_fdi_link_train()
3734 reg = FDI_RX_IIR(pipe); in ivb_manual_fdi_link_train()
3753 reg = FDI_TX_CTL(pipe); in ivb_manual_fdi_link_train()
3759 reg = FDI_RX_CTL(pipe); in ivb_manual_fdi_link_train()
3769 reg = FDI_RX_IIR(pipe); in ivb_manual_fdi_link_train()
3794 int pipe = intel_crtc->pipe; in ironlake_fdi_pll_enable() local
3799 reg = FDI_RX_CTL(pipe); in ironlake_fdi_pll_enable()
3803 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_pll_enable()
3817 reg = FDI_TX_CTL(pipe); in ironlake_fdi_pll_enable()
3831 int pipe = intel_crtc->pipe; in ironlake_fdi_pll_disable() local
3835 reg = FDI_RX_CTL(pipe); in ironlake_fdi_pll_disable()
3840 reg = FDI_TX_CTL(pipe); in ironlake_fdi_pll_disable()
3847 reg = FDI_RX_CTL(pipe); in ironlake_fdi_pll_disable()
3861 int pipe = intel_crtc->pipe; in ironlake_fdi_disable() local
3865 reg = FDI_TX_CTL(pipe); in ironlake_fdi_disable()
3870 reg = FDI_RX_CTL(pipe); in ironlake_fdi_disable()
3873 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()
3881 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); in ironlake_fdi_disable()
3884 reg = FDI_TX_CTL(pipe); in ironlake_fdi_disable()
3890 reg = FDI_RX_CTL(pipe); in ironlake_fdi_disable()
3901 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()
3924 intel_wait_for_vblank(dev, crtc->pipe); in intel_has_pending_fb_unpin()
3943 intel_crtc->pipe, in page_flip_completed()
4071 enum pipe pch_transcoder) in ironlake_pch_transcoder_set_timings()
4119 switch (intel_crtc->pipe) { in ivybridge_update_fdi_bc_bifurcation()
4151 int pipe = intel_crtc->pipe; in ironlake_pch_enable() local
4154 assert_pch_transcoder_disabled(dev_priv, pipe); in ironlake_pch_enable()
4161 I915_WRITE(FDI_RX_TUSIZE1(pipe), in ironlake_pch_enable()
4162 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); in ironlake_pch_enable()
4173 temp |= TRANS_DPLL_ENABLE(pipe); in ironlake_pch_enable()
4174 sel = TRANS_DPLLB_SEL(pipe); in ironlake_pch_enable()
4192 assert_panel_unlocked(dev_priv, pipe); in ironlake_pch_enable()
4193 ironlake_pch_transcoder_set_timings(intel_crtc, pipe); in ironlake_pch_enable()
4199 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; in ironlake_pch_enable()
4200 reg = TRANS_DP_CTL(pipe); in ironlake_pch_enable()
4230 ironlake_enable_pch_transcoder(dev_priv, pipe); in ironlake_pch_enable()
4263 i = (enum intel_dpll_id) crtc->pipe; in intel_get_shared_dpll()
4333 pipe_name(crtc->pipe)); in intel_get_shared_dpll()
4335 shared_dpll[i].crtc_mask |= 1 << crtc->pipe; in intel_get_shared_dpll()
4357 static void cpt_verify_modeset(struct drm_device *dev, int pipe) in cpt_verify_modeset() argument
4360 int dslreg = PIPEDSL(pipe); in cpt_verify_modeset()
4367 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); in cpt_verify_modeset()
4403 intel_crtc->pipe, scaler_user, *scaler_id, in skl_update_scaler()
4418 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); in skl_update_scaler()
4426 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, in skl_update_scaler()
4447 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); in skl_update_scaler_crtc()
4478 intel_plane->base.base.id, intel_crtc->pipe, in skl_update_scaler_plane()
4535 int pipe = crtc->pipe; in skylake_pfit_enable() local
4550 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | in skylake_pfit_enable()
4552 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); in skylake_pfit_enable()
4553 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); in skylake_pfit_enable()
4563 int pipe = crtc->pipe; in ironlake_pfit_enable() local
4571 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | in ironlake_pfit_enable()
4572 PF_PIPE_SEL_IVB(pipe)); in ironlake_pfit_enable()
4574 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); in ironlake_pfit_enable()
4575 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); in ironlake_pfit_enable()
4576 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); in ironlake_pfit_enable()
4589 intel_wait_for_vblank(dev, crtc->pipe); in hsw_enable_ips()
4635 intel_wait_for_vblank(dev, crtc->pipe); in hsw_disable_ips()
4644 enum pipe pipe = intel_crtc->pipe; in intel_crtc_load_lut() local
4656 assert_pll_enabled(dev_priv, pipe); in intel_crtc_load_lut()
4663 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == in intel_crtc_load_lut()
4673 palreg = PALETTE(pipe, i); in intel_crtc_load_lut()
4675 palreg = LGC_PALETTE(pipe, i); in intel_crtc_load_lut()
4721 int pipe = intel_crtc->pipe; in intel_post_enable_primary() local
4729 intel_wait_for_vblank(dev, pipe); in intel_post_enable_primary()
4747 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); in intel_post_enable_primary()
4770 int pipe = intel_crtc->pipe; in intel_pre_disable_primary() local
4779 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); in intel_pre_disable_primary()
4793 intel_wait_for_vblank(dev, pipe); in intel_pre_disable_primary()
4813 intel_wait_for_vblank(dev, crtc->pipe); in intel_post_plane_update()
4876 int pipe = intel_crtc->pipe; in intel_crtc_disable_planes() local
4888 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); in intel_crtc_disable_planes()
4897 int pipe = intel_crtc->pipe; in ironlake_crtc_enable() local
4919 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); in ironlake_crtc_enable()
4920 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); in ironlake_crtc_enable()
4932 assert_fdi_tx_disabled(dev_priv, pipe); in ironlake_crtc_enable()
4933 assert_fdi_rx_disabled(dev_priv, pipe); in ironlake_crtc_enable()
4957 cpt_verify_modeset(dev, intel_crtc->pipe); in ironlake_crtc_enable()
4963 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; in hsw_crtc_supports_ips()
4972 int pipe = intel_crtc->pipe, hsw_workaround_pipe; in haswell_crtc_enable() local
5004 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); in haswell_crtc_enable()
5066 int pipe = crtc->pipe; in ironlake_pfit_disable() local
5071 I915_WRITE(PF_CTL(pipe), 0); in ironlake_pfit_disable()
5072 I915_WRITE(PF_WIN_POS(pipe), 0); in ironlake_pfit_disable()
5073 I915_WRITE(PF_WIN_SZ(pipe), 0); in ironlake_pfit_disable()
5083 int pipe = intel_crtc->pipe; in ironlake_crtc_disable() local
5093 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); in ironlake_crtc_disable()
5107 ironlake_disable_pch_transcoder(dev_priv, pipe); in ironlake_crtc_disable()
5111 reg = TRANS_DP_CTL(pipe); in ironlake_crtc_disable()
5120 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); in ironlake_crtc_disable()
5188 assert_pipe_disabled(dev_priv, crtc->pipe); in i9xx_pfit_enable()
5195 I915_WRITE(BCLRPAT(crtc->pipe), 0); in i9xx_pfit_enable()
5303 enum pipe pipe = intel_crtc->pipe; in get_crtc_power_domains() local
5310 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); in get_crtc_power_domains()
5312 mask = BIT(POWER_DOMAIN_PIPE(pipe)); in get_crtc_power_domains()
5316 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); in get_crtc_power_domains()
5362 put_domains[to_intel_crtc(crtc)->pipe] = in modeset_update_crtc_power_domains()
6141 int pipe = intel_crtc->pipe; in valleyview_crtc_enable() local
6154 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { in valleyview_crtc_enable()
6157 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); in valleyview_crtc_enable()
6158 I915_WRITE(CHV_CANVAS(pipe), 0); in valleyview_crtc_enable()
6165 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); in valleyview_crtc_enable()
6203 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); in i9xx_set_pll_dividers()
6204 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); in i9xx_set_pll_dividers()
6213 int pipe = intel_crtc->pipe; in i9xx_crtc_enable() local
6230 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); in i9xx_crtc_enable()
6260 assert_pipe_disabled(dev_priv, crtc->pipe); in i9xx_pfit_disable()
6273 int pipe = intel_crtc->pipe; in i9xx_crtc_disable() local
6281 intel_wait_for_vblank(dev, pipe); in i9xx_crtc_disable()
6299 chv_disable_pll(dev_priv, pipe); in i9xx_crtc_disable()
6301 vlv_disable_pll(dev_priv, pipe); in i9xx_crtc_disable()
6311 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); in i9xx_crtc_disable()
6481 enum pipe pipe = 0; in intel_connector_get_hw_state() local
6484 return encoder->get_hw_state(encoder, &pipe); in intel_connector_get_hw_state()
6495 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, in ironlake_check_fdi_lanes() argument
6503 pipe_name(pipe), pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
6506 pipe_name(pipe), pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
6524 switch (pipe) { in ironlake_check_fdi_lanes()
6539 pipe_name(pipe), pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
6546 pipe_name(pipe), pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
6596 intel_crtc->pipe, pipe_config); in ironlake_fdi_compute_config()
6663 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && in intel_crtc_compute_config()
7201 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe in vlv_pllb_recal_opamp() argument
7202 pipe) in vlv_pllb_recal_opamp()
7210 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); in vlv_pllb_recal_opamp()
7213 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); in vlv_pllb_recal_opamp()
7215 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); in vlv_pllb_recal_opamp()
7218 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); in vlv_pllb_recal_opamp()
7220 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); in vlv_pllb_recal_opamp()
7222 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); in vlv_pllb_recal_opamp()
7224 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); in vlv_pllb_recal_opamp()
7227 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); in vlv_pllb_recal_opamp()
7235 int pipe = crtc->pipe; in intel_pch_transcoder_set_m_n() local
7237 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); in intel_pch_transcoder_set_m_n()
7238 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); in intel_pch_transcoder_set_m_n()
7239 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); in intel_pch_transcoder_set_m_n()
7240 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); in intel_pch_transcoder_set_m_n()
7249 int pipe = crtc->pipe; in intel_cpu_transcoder_set_m_n() local
7270 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); in intel_cpu_transcoder_set_m_n()
7271 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); in intel_cpu_transcoder_set_m_n()
7272 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); in intel_cpu_transcoder_set_m_n()
7273 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); in intel_cpu_transcoder_set_m_n()
7315 if (crtc->pipe == PIPE_B) in vlv_compute_dpll()
7330 int pipe = crtc->pipe; in vlv_prepare_pll() local
7346 if (pipe == PIPE_B) in vlv_prepare_pll()
7347 vlv_pllb_recal_opamp(dev_priv, pipe); in vlv_prepare_pll()
7350 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); in vlv_prepare_pll()
7353 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); in vlv_prepare_pll()
7355 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); in vlv_prepare_pll()
7358 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); in vlv_prepare_pll()
7372 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); in vlv_prepare_pll()
7375 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); in vlv_prepare_pll()
7381 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), in vlv_prepare_pll()
7384 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), in vlv_prepare_pll()
7389 if (pipe == PIPE_A) in vlv_prepare_pll()
7390 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
7393 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
7397 if (pipe == PIPE_A) in vlv_prepare_pll()
7398 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
7401 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
7405 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); in vlv_prepare_pll()
7410 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); in vlv_prepare_pll()
7412 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); in vlv_prepare_pll()
7422 if (crtc->pipe != PIPE_A) in chv_compute_dpll()
7434 int pipe = crtc->pipe; in chv_prepare_pll() local
7435 int dpll_reg = DPLL(crtc->pipe); in chv_prepare_pll()
7436 enum dpio_channel port = vlv_pipe_to_channel(pipe); in chv_prepare_pll()
7461 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), in chv_prepare_pll()
7468 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); in chv_prepare_pll()
7471 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), in chv_prepare_pll()
7476 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); in chv_prepare_pll()
7479 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); in chv_prepare_pll()
7484 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); in chv_prepare_pll()
7487 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); in chv_prepare_pll()
7493 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); in chv_prepare_pll()
7518 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); in chv_prepare_pll()
7520 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); in chv_prepare_pll()
7523 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); in chv_prepare_pll()
7526 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), in chv_prepare_pll()
7527 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | in chv_prepare_pll()
7543 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, in vlv_force_pll_on() argument
7547 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); in vlv_force_pll_on()
7573 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) in vlv_force_pll_off() argument
7576 chv_disable_pll(to_i915(dev), pipe); in vlv_force_pll_off()
7578 vlv_disable_pll(to_i915(dev), pipe); in vlv_force_pll_off()
7700 enum pipe pipe = intel_crtc->pipe; in intel_set_pipe_timings() local
7753 (pipe == PIPE_B || pipe == PIPE_C)) in intel_set_pipe_timings()
7754 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); in intel_set_pipe_timings()
7759 I915_WRITE(PIPESRC(pipe), in intel_set_pipe_timings()
7798 tmp = I915_READ(PIPESRC(crtc->pipe)); in intel_get_pipe_timings()
7838 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in i9xx_set_pipeconf()
7839 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in i9xx_set_pipeconf()
7840 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; in i9xx_set_pipeconf()
7889 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); in i9xx_set_pipeconf()
7890 POSTING_READ(PIPECONF(intel_crtc->pipe)); in i9xx_set_pipeconf()
7989 if (crtc->pipe != PIPE_B) in i9xx_get_pfit_config()
7992 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) in i9xx_get_pfit_config()
8008 int pipe = pipe_config->cpu_transcoder; in vlv_crtc_clock_get() local
8018 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); in vlv_crtc_clock_get()
8037 int pipe = crtc->pipe, plane = crtc->plane; in i9xx_get_initial_plane_config() local
8078 val = I915_READ(PIPESRC(pipe)); in i9xx_get_initial_plane_config()
8082 val = I915_READ(DSPSTRIDE(pipe)); in i9xx_get_initial_plane_config()
8092 pipe_name(pipe), plane, fb->width, fb->height, in i9xx_get_initial_plane_config()
8104 int pipe = pipe_config->cpu_transcoder; in chv_crtc_clock_get() local
8105 enum dpio_channel port = vlv_pipe_to_channel(pipe); in chv_crtc_clock_get()
8111 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); in chv_crtc_clock_get()
8112 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); in chv_crtc_clock_get()
8113 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); in chv_crtc_clock_get()
8114 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); in chv_crtc_clock_get()
8115 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); in chv_crtc_clock_get()
8137 POWER_DOMAIN_PIPE(crtc->pipe))) in i9xx_get_pipe_config()
8140 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in i9xx_get_pipe_config()
8143 tmp = I915_READ(PIPECONF(crtc->pipe)); in i9xx_get_pipe_config()
8174 tmp = I915_READ(DPLL_MD(crtc->pipe)); in i9xx_get_pipe_config()
8180 tmp = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
8190 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
8200 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); in i9xx_get_pipe_config()
8201 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); in i9xx_get_pipe_config()
8615 int pipe = intel_crtc->pipe; in ironlake_set_pipeconf() local
8649 I915_WRITE(PIPECONF(pipe), val); in ironlake_set_pipeconf()
8650 POSTING_READ(PIPECONF(pipe)); in ironlake_set_pipeconf()
8665 int pipe = intel_crtc->pipe; in intel_set_pipe_csc() local
8683 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); in intel_set_pipe_csc()
8684 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); in intel_set_pipe_csc()
8686 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); in intel_set_pipe_csc()
8687 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); in intel_set_pipe_csc()
8689 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); in intel_set_pipe_csc()
8690 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); in intel_set_pipe_csc()
8692 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); in intel_set_pipe_csc()
8693 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); in intel_set_pipe_csc()
8694 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); in intel_set_pipe_csc()
8702 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); in intel_set_pipe_csc()
8703 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); in intel_set_pipe_csc()
8704 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); in intel_set_pipe_csc()
8706 I915_WRITE(PIPE_CSC_MODE(pipe), 0); in intel_set_pipe_csc()
8713 I915_WRITE(PIPE_CSC_MODE(pipe), mode); in intel_set_pipe_csc()
8722 enum pipe pipe = intel_crtc->pipe; in haswell_set_pipeconf() local
8739 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); in haswell_set_pipeconf()
8740 POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); in haswell_set_pipeconf()
8766 I915_WRITE(PIPEMISC(pipe), val); in haswell_set_pipeconf()
8964 pipe_name(crtc->pipe)); in ironlake_crtc_compute_clock()
8982 enum pipe pipe = crtc->pipe; in intel_pch_transcoder_get_m_n() local
8984 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); in intel_pch_transcoder_get_m_n()
8985 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); in intel_pch_transcoder_get_m_n()
8986 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) in intel_pch_transcoder_get_m_n()
8988 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); in intel_pch_transcoder_get_m_n()
8989 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) in intel_pch_transcoder_get_m_n()
9000 enum pipe pipe = crtc->pipe; in intel_cpu_transcoder_get_m_n() local
9025 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); in intel_cpu_transcoder_get_m_n()
9026 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); in intel_cpu_transcoder_get_m_n()
9027 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) in intel_cpu_transcoder_get_m_n()
9029 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); in intel_cpu_transcoder_get_m_n()
9030 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) in intel_cpu_transcoder_get_m_n()
9065 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); in skylake_get_pfit_config()
9069 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); in skylake_get_pfit_config()
9070 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); in skylake_get_pfit_config()
9090 int pipe = crtc->pipe; in skylake_get_initial_plane_config() local
9104 val = I915_READ(PLANE_CTL(pipe, 0)); in skylake_get_initial_plane_config()
9135 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; in skylake_get_initial_plane_config()
9138 offset = I915_READ(PLANE_OFFSET(pipe, 0)); in skylake_get_initial_plane_config()
9140 val = I915_READ(PLANE_SIZE(pipe, 0)); in skylake_get_initial_plane_config()
9144 val = I915_READ(PLANE_STRIDE(pipe, 0)); in skylake_get_initial_plane_config()
9156 pipe_name(pipe), fb->width, fb->height, in skylake_get_initial_plane_config()
9174 tmp = I915_READ(PF_CTL(crtc->pipe)); in ironlake_get_pfit_config()
9178 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); in ironlake_get_pfit_config()
9179 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); in ironlake_get_pfit_config()
9186 PF_PIPE_SEL_IVB(crtc->pipe)); in ironlake_get_pfit_config()
9198 int pipe = crtc->pipe; in ironlake_get_initial_plane_config() local
9204 val = I915_READ(DSPCNTR(pipe)); in ironlake_get_initial_plane_config()
9228 base = I915_READ(DSPSURF(pipe)) & 0xfffff000; in ironlake_get_initial_plane_config()
9230 offset = I915_READ(DSPOFFSET(pipe)); in ironlake_get_initial_plane_config()
9233 offset = I915_READ(DSPTILEOFF(pipe)); in ironlake_get_initial_plane_config()
9235 offset = I915_READ(DSPLINOFF(pipe)); in ironlake_get_initial_plane_config()
9239 val = I915_READ(PIPESRC(pipe)); in ironlake_get_initial_plane_config()
9243 val = I915_READ(DSPSTRIDE(pipe)); in ironlake_get_initial_plane_config()
9253 pipe_name(pipe), fb->width, fb->height, in ironlake_get_initial_plane_config()
9268 POWER_DOMAIN_PIPE(crtc->pipe))) in ironlake_get_pipe_config()
9271 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in ironlake_get_pipe_config()
9274 tmp = I915_READ(PIPECONF(crtc->pipe)); in ironlake_get_pipe_config()
9298 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { in ironlake_get_pipe_config()
9303 tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); in ironlake_get_pipe_config()
9311 (enum intel_dpll_id) crtc->pipe; in ironlake_get_pipe_config()
9314 if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) in ironlake_get_pipe_config()
9349 pipe_name(crtc->pipe)); in assert_can_disable_lcpll()
9856 POWER_DOMAIN_PIPE(crtc->pipe))) in haswell_get_pipe_config()
9859 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in haswell_get_pipe_config()
9864 enum pipe trans_edp_pipe; in haswell_get_pipe_config()
9880 if (trans_edp_pipe == crtc->pipe) in haswell_get_pipe_config()
9900 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); in haswell_get_pipe_config()
9995 int pipe = intel_crtc->pipe; in i9xx_update_cursor() local
10014 cntl |= pipe << 28; /* Connect to correct pipe */ in i9xx_update_cursor()
10024 I915_WRITE(CURCNTR(pipe), cntl); in i9xx_update_cursor()
10025 POSTING_READ(CURCNTR(pipe)); in i9xx_update_cursor()
10030 I915_WRITE(CURBASE(pipe), base); in i9xx_update_cursor()
10031 POSTING_READ(CURBASE(pipe)); in i9xx_update_cursor()
10043 int pipe = intel_crtc->pipe; in intel_crtc_update_cursor() local
10075 I915_WRITE(CURPOS(pipe), pos); in intel_crtc_update_cursor()
10445 intel_wait_for_vblank(dev, intel_crtc->pipe); in intel_get_load_detect_pipe()
10548 int pipe = pipe_config->cpu_transcoder; in i9xx_crtc_clock_get() local
10598 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); in i9xx_crtc_clock_get()
10683 enum pipe pipe = intel_crtc->pipe; in intel_crtc_mode_get() local
10696 pipe_config.cpu_transcoder = (enum transcoder) pipe; in intel_crtc_mode_get()
10698 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); in intel_crtc_mode_get()
10699 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); in intel_crtc_mode_get()
10700 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); in intel_crtc_mode_get()
10824 void intel_finish_page_flip(struct drm_device *dev, int pipe) in intel_finish_page_flip() argument
10827 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in intel_finish_page_flip()
10882 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), in page_flip_finished()
11016 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; in intel_gen4_queue_flip()
11052 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; in intel_gen6_queue_flip()
11187 const enum pipe pipe = intel_crtc->pipe; in skl_do_mmio_flip() local
11190 ctl = I915_READ(PLANE_CTL(pipe, 0)); in skl_do_mmio_flip()
11220 I915_WRITE(PLANE_CTL(pipe, 0), ctl); in skl_do_mmio_flip()
11221 I915_WRITE(PLANE_STRIDE(pipe, 0), stride); in skl_do_mmio_flip()
11223 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); in skl_do_mmio_flip()
11224 POSTING_READ(PLANE_SURF(pipe, 0)); in skl_do_mmio_flip()
11372 void intel_check_page_flip(struct drm_device *dev, int pipe) in intel_check_page_flip() argument
11375 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in intel_check_page_flip()
11388 work->flip_queued_vblank, drm_vblank_count(dev, pipe)); in intel_check_page_flip()
11393 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) in intel_check_page_flip()
11409 enum pipe pipe = intel_crtc->pipe; in intel_crtc_page_flip() local
11494 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; in intel_crtc_page_flip()
11623 drm_send_vblank_event(dev, pipe, event); in intel_crtc_page_flip()
12007 context, pipe_config, pipe_name(crtc->pipe)); in intel_dump_pipe_config()
12101 if (intel_plane->pipe != crtc->pipe) in intel_dump_pipe_config()
12110 plane->base.id, intel_plane->pipe, in intel_dump_pipe_config()
12118 plane->base.id, intel_plane->pipe, in intel_dump_pipe_config()
12229 (enum transcoder) to_intel_crtc(crtc)->pipe; in intel_modeset_pipe_config()
12360 if (mask & (1 <<(intel_crtc)->pipe))
12651 const enum pipe pipe = intel_crtc->pipe; in check_wm_state() local
12657 for_each_plane(dev_priv, pipe, plane) { in check_wm_state()
12658 hw_entry = &hw_ddb.plane[pipe][plane]; in check_wm_state()
12659 sw_entry = &sw_ddb->plane[pipe][plane]; in check_wm_state()
12666 pipe_name(pipe), plane + 1, in check_wm_state()
12672 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; in check_wm_state()
12673 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; in check_wm_state()
12680 pipe_name(pipe), in check_wm_state()
12715 enum pipe pipe; in check_encoder_state() local
12739 active = encoder->get_hw_state(encoder, &pipe); in check_encoder_state()
12742 pipe_name(pipe)); in check_encoder_state()
12778 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in check_crtc_state()
12779 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in check_crtc_state()
12791 enum pipe pipe; in check_crtc_state() local
12793 active = encoder->get_hw_state(encoder, &pipe); in check_crtc_state()
12798 I915_STATE_WARN(active && intel_crtc->pipe != pipe, in check_crtc_state()
12800 pipe_name(pipe)); in check_crtc_state()
12960 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe); in intel_modeset_clear_plls()
12977 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; in haswell_mode_set_planes_workaround()
12992 first_pipe = intel_crtc->pipe; in haswell_mode_set_planes_workaround()
13018 enabled_pipe = intel_crtc->pipe; in haswell_mode_set_planes_workaround()
13393 assert_pch_transcoder_disabled(dev_priv, crtc->pipe); in ibx_pch_dpll_disable()
13663 int pipe) in intel_primary_plane_create() argument
13687 primary->pipe = pipe; in intel_primary_plane_create()
13688 primary->plane = pipe; in intel_primary_plane_create()
13689 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); in intel_primary_plane_create()
13694 primary->plane = !pipe; in intel_primary_plane_create()
13746 enum pipe pipe = to_intel_plane(plane)->pipe; in intel_check_cursor_plane() local
13790 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && in intel_check_cursor_plane()
13833 int pipe) in intel_cursor_plane_create() argument
13851 cursor->pipe = pipe; in intel_cursor_plane_create()
13852 cursor->plane = pipe; in intel_cursor_plane_create()
13853 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); in intel_cursor_plane_create()
13900 static void intel_crtc_init(struct drm_device *dev, int pipe) in intel_crtc_init() argument
13922 if (pipe == PIPE_C) in intel_crtc_init()
13930 primary = intel_primary_plane_create(dev, pipe); in intel_crtc_init()
13934 cursor = intel_cursor_plane_create(dev, pipe); in intel_crtc_init()
13954 intel_crtc->pipe = pipe; in intel_crtc_init()
13955 intel_crtc->plane = pipe; in intel_crtc_init()
13958 intel_crtc->plane = !pipe; in intel_crtc_init()
13967 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || in intel_crtc_init()
13970 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; in intel_crtc_init()
13974 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); in intel_crtc_init()
13986 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) in intel_get_pipe_from_connector()
13996 return to_intel_crtc(encoder->crtc)->pipe; in intel_get_pipe_from_connector()
14014 pipe_from_crtc_id->pipe = crtc->pipe; in intel_get_pipe_from_crtc_id()
14878 enum pipe pipe; in intel_modeset_init() local
14949 for_each_pipe(dev_priv, pipe) { in intel_modeset_init()
14950 intel_crtc_init(dev, pipe); in intel_modeset_init()
14951 for_each_sprite(dev_priv, pipe, sprite) { in intel_modeset_init()
14952 ret = intel_plane_init(dev, pipe, sprite); in intel_modeset_init()
14955 pipe_name(pipe), sprite_name(pipe, sprite), ret); in intel_modeset_init()
15036 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) in intel_check_plane_mapping()
15099 crtc->pipe == PIPE_A && !crtc->active) { in intel_sanitize_crtc()
15263 enum pipe pipe; in intel_modeset_readout_hw_state() local
15297 pll->config.crtc_mask |= 1 << crtc->pipe; in intel_modeset_readout_hw_state()
15309 pipe = 0; in intel_modeset_readout_hw_state()
15311 if (encoder->get_hw_state(encoder, &pipe)) { in intel_modeset_readout_hw_state()
15312 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); in intel_modeset_readout_hw_state()
15323 pipe_name(pipe)); in intel_modeset_readout_hw_state()
15381 enum pipe pipe; in intel_modeset_setup_hw_state() local
15393 for_each_pipe(dev_priv, pipe) { in intel_modeset_setup_hw_state()
15394 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); in intel_modeset_setup_hw_state()
15515 to_intel_crtc(c)->pipe); in intel_modeset_gem_init()
15646 } pipe[I915_MAX_PIPES]; member
15697 error->pipe[i].power_domain_on = in intel_display_capture_error_state()
15700 if (!error->pipe[i].power_domain_on) in intel_display_capture_error_state()
15720 error->pipe[i].source = I915_READ(PIPESRC(i)); in intel_display_capture_error_state()
15723 error->pipe[i].stat = I915_READ(PIPESTAT(i)); in intel_display_capture_error_state()
15773 error->pipe[i].power_domain_on ? "on" : "off"); in intel_display_print_error_state()
15774 err_printf(m, " SRC: %08x\n", error->pipe[i].source); in intel_display_print_error_state()
15775 err_printf(m, " STAT: %08x\n", error->pipe[i].stat); in intel_display_print_error_state()