133 	intel_p2_t	    p2;  member
245 	.p2 = { .dot_limit = 165000,
258 	.p2 = { .dot_limit = 165000,
271 	.p2 = { .dot_limit = 165000,
284 	.p2 = { .dot_limit = 200000,
297 	.p2 = { .dot_limit = 112000,
311 	.p2 = { .dot_limit = 270000,
326 	.p2 = { .dot_limit = 165000,
339 	.p2 = { .dot_limit = 0,
353 	.p2 = { .dot_limit = 0,
369 	.p2 = { .dot_limit = 200000,
382 	.p2 = { .dot_limit = 112000,
400 	.p2 = { .dot_limit = 225000,
413 	.p2 = { .dot_limit = 225000,
426 	.p2 = { .dot_limit = 225000,
440 	.p2 = { .dot_limit = 225000,
453 	.p2 = { .dot_limit = 225000,
470 	.p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
486 	.p2 = {	.p2_slow = 1, .p2_fast = 14 },
498 	.p2 = { .p2_slow = 1, .p2_fast = 20 },
648 	clock->p = clock->p1 * clock->p2;  in pnv_calc_dpll_params()
665 	clock->p = clock->p1 * clock->p2;  in i9xx_calc_dpll_params()
677 	clock->p = clock->p1 * clock->p2;  in vlv_calc_dpll_params()
689 	clock->p = clock->p1 * clock->p2;  in chv_calc_dpll_params()
754 			return limit->p2.p2_fast;  in i9xx_select_p2_div()
756 			return limit->p2.p2_slow;  in i9xx_select_p2_div()
758 		if (target < limit->p2.dot_limit)  in i9xx_select_p2_div()
759 			return limit->p2.p2_slow;  in i9xx_select_p2_div()
761 			return limit->p2.p2_fast;  in i9xx_select_p2_div()
777 	clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);  in i9xx_find_best_dpll()
824 	clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);  in pnv_find_best_dpll()
872 	clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);  in g4x_find_best_dpll()
966 			for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;  in vlv_find_best_dpll()
967 			     clock.p2 -= clock.p2 > 10 ? 2 : 1) {  in vlv_find_best_dpll()
968 				clock.p = clock.p1 * clock.p2;  in vlv_find_best_dpll()
1024 		for (clock.p2 = limit->p2.p2_fast;  in chv_find_best_dpll()
1025 				clock.p2 >= limit->p2.p2_slow;  in chv_find_best_dpll()
1026 				clock.p2 -= clock.p2 > 10 ? 2 : 1) {  in chv_find_best_dpll()
1029 			clock.p = clock.p1 * clock.p2;  in chv_find_best_dpll()
7341 	bestp2 = pipe_config->dpll.p2;  in vlv_prepare_pll()
7447 	bestp2 = pipe_config->dpll.p2;  in chv_prepare_pll()
7623 	switch (clock->p2) {  in i9xx_compute_dpll()
7679 		if (clock->p2 == 4)  in i8xx_compute_dpll()
7955 		crtc_state->dpll.p2 = clock.p2;  in i9xx_crtc_compute_clock()
8025 	clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;  in vlv_crtc_clock_get()
8124 	clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;  in chv_crtc_clock_get()
8888 	switch (crtc_state->dpll.p2) {  in ironlake_compute_dpll()
8941 		crtc_state->dpll.p2 = clock.p2;  in ironlake_crtc_compute_clock()
10579 			clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?  in i9xx_crtc_clock_get()
10583 			clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?  in i9xx_crtc_clock_get()
10605 				clock.p2 = 7;  in i9xx_crtc_clock_get()
10607 				clock.p2 = 14;  in i9xx_crtc_clock_get()
10616 				clock.p2 = 4;  in i9xx_crtc_clock_get()
10618 				clock.p2 = 2;  in i9xx_crtc_clock_get()