Lines Matching refs:mdiv
7331 u32 mdiv; in vlv_prepare_pll() local
7361 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); in vlv_prepare_pll()
7362 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); in vlv_prepare_pll()
7363 mdiv |= ((bestn << DPIO_N_SHIFT)); in vlv_prepare_pll()
7364 mdiv |= (1 << DPIO_K_SHIFT); in vlv_prepare_pll()
7371 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); in vlv_prepare_pll()
7372 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); in vlv_prepare_pll()
7374 mdiv |= DPIO_ENABLE_CALIBRATION; in vlv_prepare_pll()
7375 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); in vlv_prepare_pll()
8010 u32 mdiv; in vlv_crtc_clock_get() local
8018 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); in vlv_crtc_clock_get()
8021 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; in vlv_crtc_clock_get()
8022 clock.m2 = mdiv & DPIO_M2DIV_MASK; in vlv_crtc_clock_get()
8023 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; in vlv_crtc_clock_get()
8024 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; in vlv_crtc_clock_get()
8025 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; in vlv_crtc_clock_get()