132 	intel_range_t   dot, vco, n, m, m1, m2, p, p1;  member
242 	.m2 = { .min = 6, .max = 16 },
255 	.m2 = { .min = 6, .max = 16 },
268 	.m2 = { .min = 6, .max = 16 },
281 	.m2 = { .min = 3, .max = 7 },
294 	.m2 = { .min = 3, .max = 7 },
308 	.m2 = { .min = 5, .max = 11 },
323 	.m2 = { .min = 5, .max = 11 },
336 	.m2 = { .min = 5, .max = 11 },
350 	.m2 = { .min = 5, .max = 11 },
366 	.m2 = { .min = 0, .max = 254 },
379 	.m2 = { .min = 0, .max = 254 },
397 	.m2 = { .min = 5, .max = 9 },
410 	.m2 = { .min = 5, .max = 9 },
423 	.m2 = { .min = 5, .max = 9 },
437 	.m2 = { .min = 5, .max = 9 },
450 	.m2 = { .min = 5, .max = 9 },
468 	.m2 = { .min = 11, .max = 156 },
484 	.m2 = { .min = 24 << 22, .max = 175 << 22 },
496 	.m2 = { .min = 2 << 22, .max = 255 << 22 },
647 	clock->m = clock->m2 + 2;  in pnv_calc_dpll_params()
659 	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);  in i9xx_dpll_compute_m()
676 	clock->m = clock->m1 * clock->m2;  in vlv_calc_dpll_params()
688 	clock->m = clock->m1 * clock->m2;  in chv_calc_dpll_params()
713 	if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)  in intel_PLL_is_valid()
719 		if (clock->m1 <= clock->m2)  in intel_PLL_is_valid()
781 		for (clock.m2 = limit->m2.min;  in i9xx_find_best_dpll()
782 		     clock.m2 <= limit->m2.max; clock.m2++) {  in i9xx_find_best_dpll()
783 			if (clock.m2 >= clock.m1)  in i9xx_find_best_dpll()
828 		for (clock.m2 = limit->m2.min;  in pnv_find_best_dpll()
829 		     clock.m2 <= limit->m2.max; clock.m2++) {  in pnv_find_best_dpll()
880 			for (clock.m2 = limit->m2.max;  in g4x_find_best_dpll()
881 			     clock.m2 >= limit->m2.min; clock.m2--) {  in g4x_find_best_dpll()
973 					clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,  in vlv_find_best_dpll()
1009 	uint64_t m2;  in chv_find_best_dpll()  local
1031 			m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *  in chv_find_best_dpll()
1034 			if (m2 > INT_MAX/clock.m1)  in chv_find_best_dpll()
1037 			clock.m2 = m2;  in chv_find_best_dpll()
7164 	return (1 << dpll->n) << 16 | dpll->m2;  in pnv_dpll_compute_fp()
7169 	return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;  in i9xx_dpll_compute_fp()
7339 	bestm2 = pipe_config->dpll.m2;  in vlv_prepare_pll()
7443 	bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;  in chv_prepare_pll()
7445 	bestm2 = pipe_config->dpll.m2 >> 22;  in chv_prepare_pll()
7953 		crtc_state->dpll.m2 = clock.m2;  in i9xx_crtc_compute_clock()
8022 	clock.m2 = mdiv & DPIO_M2DIV_MASK;  in vlv_crtc_clock_get()
8119 	clock.m2 = (pll_dw0 & 0xff) << 22;  in chv_crtc_clock_get()
8121 		clock.m2 |= pll_dw2 & 0x3fffff;  in chv_crtc_clock_get()
8939 		crtc_state->dpll.m2 = clock.m2;  in ironlake_crtc_compute_clock()
10563 		clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;  in i9xx_crtc_clock_get()
10566 		clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;  in i9xx_crtc_clock_get()
12364 		  unsigned int m2, unsigned int n2,  in intel_compare_m_n()  argument
12367 	if (m == m2 && n == n2)  in intel_compare_m_n()
12370 	if (exact || !m || !n || !m2 || !n2)  in intel_compare_m_n()
12375 	if (m > m2) {  in intel_compare_m_n()
12376 		while (m > m2) {  in intel_compare_m_n()
12377 			m2 <<= 1;  in intel_compare_m_n()
12380 	} else if (m < m2) {  in intel_compare_m_n()
12381 		while (m < m2) {  in intel_compare_m_n()
12387 	return m == m2 && n == n2;  in intel_compare_m_n()