Lines Matching refs:intel_crtc
88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
105 static void vlv_prepare_pll(struct intel_crtc *crtc,
107 static void chv_prepare_pll(struct intel_crtc *crtc,
111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
510 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) in intel_pipe_has_type()
951 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in vlv_find_best_dpll()
1005 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in chv_find_best_dpll()
1068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_active() local
1083 return intel_crtc->active && crtc->primary->state->fb && in intel_crtc_active()
1084 intel_crtc->config->base.adjusted_mode.crtc_clock; in intel_crtc_active()
1091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_pipe_to_cpu_transcoder() local
1093 return intel_crtc->config->cpu_transcoder; in intel_pipe_to_cpu_transcoder()
1131 static void intel_wait_for_pipe_off(struct intel_crtc *crtc) in intel_wait_for_pipe_off()
1190 intel_crtc_to_shared_dpll(struct intel_crtc *crtc) in intel_crtc_to_shared_dpll()
1598 static void vlv_enable_pll(struct intel_crtc *crtc, in vlv_enable_pll()
1637 static void chv_enable_pll(struct intel_crtc *crtc, in chv_enable_pll()
1678 struct intel_crtc *crtc; in intel_num_dvo_pipes()
1688 static void i9xx_enable_pll(struct intel_crtc *crtc) in i9xx_enable_pll()
1763 static void i9xx_disable_pll(struct intel_crtc *crtc) in i9xx_disable_pll()
1866 static void intel_prepare_shared_dpll(struct intel_crtc *crtc) in intel_prepare_shared_dpll()
1893 static void intel_enable_shared_dpll(struct intel_crtc *crtc) in intel_enable_shared_dpll()
1923 static void intel_disable_shared_dpll(struct intel_crtc *crtc) in intel_disable_shared_dpll()
1965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_enable_pch_transcoder() local
1973 intel_crtc_to_shared_dpll(intel_crtc)); in ironlake_enable_pch_transcoder()
1999 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) in ironlake_enable_pch_transcoder()
2008 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) in ironlake_enable_pch_transcoder()
2105 static void intel_enable_pipe(struct intel_crtc *crtc) in intel_enable_pipe()
2169 static void intel_disable_pipe(struct intel_crtc *crtc) in intel_disable_pipe()
2528 intel_alloc_initial_plane_obj(struct intel_crtc *crtc, in intel_alloc_initial_plane_obj()
2601 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, in intel_find_initial_plane_obj() argument
2604 struct drm_device *dev = intel_crtc->base.dev; in intel_find_initial_plane_obj()
2607 struct intel_crtc *i; in intel_find_initial_plane_obj()
2609 struct drm_plane *primary = intel_crtc->base.primary; in intel_find_initial_plane_obj()
2611 struct drm_crtc_state *crtc_state = intel_crtc->base.state; in intel_find_initial_plane_obj()
2618 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { in intel_find_initial_plane_obj()
2632 if (c == &intel_crtc->base) in intel_find_initial_plane_obj()
2658 intel_pre_disable_primary(&intel_crtc->base); in intel_find_initial_plane_obj()
2659 intel_plane->disable_plane(primary, &intel_crtc->base); in intel_find_initial_plane_obj()
2680 primary->crtc = primary->state->crtc = &intel_crtc->base; in intel_find_initial_plane_obj()
2681 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); in intel_find_initial_plane_obj()
2691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i9xx_update_primary_plane() local
2695 int plane = intel_crtc->plane; in i9xx_update_primary_plane()
2722 if (intel_crtc->pipe == PIPE_B) in i9xx_update_primary_plane()
2729 ((intel_crtc->config->pipe_src_h - 1) << 16) | in i9xx_update_primary_plane()
2730 (intel_crtc->config->pipe_src_w - 1)); in i9xx_update_primary_plane()
2734 ((intel_crtc->config->pipe_src_h - 1) << 16) | in i9xx_update_primary_plane()
2735 (intel_crtc->config->pipe_src_w - 1)); in i9xx_update_primary_plane()
2776 intel_crtc->dspaddr_offset = in i9xx_update_primary_plane()
2781 linear_offset -= intel_crtc->dspaddr_offset; in i9xx_update_primary_plane()
2783 intel_crtc->dspaddr_offset = linear_offset; in i9xx_update_primary_plane()
2789 x += (intel_crtc->config->pipe_src_w - 1); in i9xx_update_primary_plane()
2790 y += (intel_crtc->config->pipe_src_h - 1); in i9xx_update_primary_plane()
2795 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + in i9xx_update_primary_plane()
2796 (intel_crtc->config->pipe_src_w - 1) * pixel_size; in i9xx_update_primary_plane()
2799 intel_crtc->adjusted_x = x; in i9xx_update_primary_plane()
2800 intel_crtc->adjusted_y = y; in i9xx_update_primary_plane()
2807 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); in i9xx_update_primary_plane()
2821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_update_primary_plane() local
2825 int plane = intel_crtc->plane; in ironlake_update_primary_plane()
2881 intel_crtc->dspaddr_offset = in ironlake_update_primary_plane()
2886 linear_offset -= intel_crtc->dspaddr_offset; in ironlake_update_primary_plane()
2891 x += (intel_crtc->config->pipe_src_w - 1); in ironlake_update_primary_plane()
2892 y += (intel_crtc->config->pipe_src_h - 1); in ironlake_update_primary_plane()
2897 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + in ironlake_update_primary_plane()
2898 (intel_crtc->config->pipe_src_w - 1) * pixel_size; in ironlake_update_primary_plane()
2902 intel_crtc->adjusted_x = x; in ironlake_update_primary_plane()
2903 intel_crtc->adjusted_y = y; in ironlake_update_primary_plane()
2909 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); in ironlake_update_primary_plane()
2979 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) in skl_detach_scaler() argument
2981 struct drm_device *dev = intel_crtc->base.dev; in skl_detach_scaler()
2984 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); in skl_detach_scaler()
2985 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); in skl_detach_scaler()
2986 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); in skl_detach_scaler()
2992 static void skl_detach_scalers(struct intel_crtc *intel_crtc) in skl_detach_scalers() argument
2997 scaler_state = &intel_crtc->config->scaler_state; in skl_detach_scalers()
3000 for (i = 0; i < intel_crtc->num_scalers; i++) { in skl_detach_scalers()
3002 skl_detach_scaler(intel_crtc, i); in skl_detach_scalers()
3093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in skylake_update_primary_plane() local
3097 int pipe = intel_crtc->pipe; in skylake_update_primary_plane()
3103 struct intel_crtc_state *crtc_state = intel_crtc->config; in skylake_update_primary_plane()
3164 intel_crtc->adjusted_x = x_offset; in skylake_update_primary_plane()
3165 intel_crtc->adjusted_y = y_offset; in skylake_update_primary_plane()
3213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_complete_page_flips() local
3214 enum plane plane = intel_crtc->plane; in intel_complete_page_flips()
3339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_has_pending_flip() local
3343 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) in intel_crtc_has_pending_flip()
3353 static void intel_update_pipe_config(struct intel_crtc *crtc, in intel_update_pipe_config()
3402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_fdi_normal_train() local
3403 int pipe = intel_crtc->pipe; in intel_fdi_normal_train()
3444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_fdi_link_train() local
3445 int pipe = intel_crtc->pipe; in ironlake_fdi_link_train()
3465 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); in ironlake_fdi_link_train()
3544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in gen6_fdi_link_train() local
3545 int pipe = intel_crtc->pipe; in gen6_fdi_link_train()
3563 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); in gen6_fdi_link_train()
3676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ivb_manual_fdi_link_train() local
3677 int pipe = intel_crtc->pipe; in ivb_manual_fdi_link_train()
3714 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); in ivb_manual_fdi_link_train()
3790 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) in ironlake_fdi_pll_enable() argument
3792 struct drm_device *dev = intel_crtc->base.dev; in ironlake_fdi_pll_enable()
3794 int pipe = intel_crtc->pipe; in ironlake_fdi_pll_enable()
3802 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); in ironlake_fdi_pll_enable()
3827 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) in ironlake_fdi_pll_disable() argument
3829 struct drm_device *dev = intel_crtc->base.dev; in ironlake_fdi_pll_disable()
3831 int pipe = intel_crtc->pipe; in ironlake_fdi_pll_disable()
3860 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_fdi_disable() local
3861 int pipe = intel_crtc->pipe; in ironlake_fdi_disable()
3910 struct intel_crtc *crtc; in intel_has_pending_fb_unpin()
3932 static void page_flip_completed(struct intel_crtc *intel_crtc) in page_flip_completed() argument
3934 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); in page_flip_completed()
3935 struct intel_unpin_work *work = intel_crtc->unpin_work; in page_flip_completed()
3939 intel_crtc->unpin_work = NULL; in page_flip_completed()
3942 drm_send_vblank_event(intel_crtc->base.dev, in page_flip_completed()
3943 intel_crtc->pipe, in page_flip_completed()
3946 drm_crtc_vblank_put(&intel_crtc->base); in page_flip_completed()
3951 trace_i915_flip_complete(intel_crtc->plane, in page_flip_completed()
3964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_wait_for_pending_flips() local
3967 if (intel_crtc->unpin_work) { in intel_crtc_wait_for_pending_flips()
3969 page_flip_completed(intel_crtc); in intel_crtc_wait_for_pending_flips()
4070 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, in ironlake_pch_transcoder_set_timings()
4115 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) in ivybridge_update_fdi_bc_bifurcation() argument
4117 struct drm_device *dev = intel_crtc->base.dev; in ivybridge_update_fdi_bc_bifurcation()
4119 switch (intel_crtc->pipe) { in ivybridge_update_fdi_bc_bifurcation()
4123 if (intel_crtc->config->fdi_lanes > 2) in ivybridge_update_fdi_bc_bifurcation()
4150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_pch_enable() local
4151 int pipe = intel_crtc->pipe; in ironlake_pch_enable()
4157 ivybridge_update_fdi_bc_bifurcation(intel_crtc); in ironlake_pch_enable()
4175 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) in ironlake_pch_enable()
4189 intel_enable_shared_dpll(intel_crtc); in ironlake_pch_enable()
4193 ironlake_pch_transcoder_set_timings(intel_crtc, pipe); in ironlake_pch_enable()
4198 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { in ironlake_pch_enable()
4237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in lpt_pch_enable() local
4238 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; in lpt_pch_enable()
4245 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); in lpt_pch_enable()
4250 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, in intel_get_shared_dpll()
4378 struct intel_crtc *intel_crtc = in skl_update_scaler() local
4403 intel_crtc->pipe, scaler_user, *scaler_id, in skl_update_scaler()
4418 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); in skl_update_scaler()
4426 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, in skl_update_scaler()
4443 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); in skl_update_scaler_crtc() local
4447 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); in skl_update_scaler_crtc()
4469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); in skl_update_scaler_plane() local
4478 intel_plane->base.base.id, intel_crtc->pipe, in skl_update_scaler_plane()
4523 static void skylake_scaler_disable(struct intel_crtc *crtc) in skylake_scaler_disable()
4531 static void skylake_pfit_enable(struct intel_crtc *crtc) in skylake_pfit_enable()
4559 static void ironlake_pfit_enable(struct intel_crtc *crtc) in ironlake_pfit_enable()
4580 void hsw_enable_ips(struct intel_crtc *crtc) in hsw_enable_ips()
4613 void hsw_disable_ips(struct intel_crtc *crtc) in hsw_disable_ips()
4643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_load_lut() local
4644 enum pipe pipe = intel_crtc->pipe; in intel_crtc_load_lut()
4653 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) in intel_crtc_load_lut()
4662 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && in intel_crtc_load_lut()
4665 hsw_disable_ips(intel_crtc); in intel_crtc_load_lut()
4678 (intel_crtc->lut_r[i] << 16) | in intel_crtc_load_lut()
4679 (intel_crtc->lut_g[i] << 8) | in intel_crtc_load_lut()
4680 intel_crtc->lut_b[i]); in intel_crtc_load_lut()
4684 hsw_enable_ips(intel_crtc); in intel_crtc_load_lut()
4687 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) in intel_crtc_dpms_overlay_disable() argument
4689 if (intel_crtc->overlay) { in intel_crtc_dpms_overlay_disable()
4690 struct drm_device *dev = intel_crtc->base.dev; in intel_crtc_dpms_overlay_disable()
4695 (void) intel_overlay_switch_off(intel_crtc->overlay); in intel_crtc_dpms_overlay_disable()
4720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_post_enable_primary() local
4721 int pipe = intel_crtc->pipe; in intel_post_enable_primary()
4737 hsw_enable_ips(intel_crtc); in intel_post_enable_primary()
4769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_pre_disable_primary() local
4770 int pipe = intel_crtc->pipe; in intel_pre_disable_primary()
4802 hsw_disable_ips(intel_crtc); in intel_pre_disable_primary()
4805 static void intel_post_plane_update(struct intel_crtc *crtc) in intel_post_plane_update()
4836 static void intel_pre_plane_update(struct intel_crtc *crtc) in intel_pre_plane_update()
4874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_disable_planes() local
4876 int pipe = intel_crtc->pipe; in intel_crtc_disable_planes()
4878 intel_crtc_dpms_overlay_disable(intel_crtc); in intel_crtc_disable_planes()
4895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_crtc_enable() local
4897 int pipe = intel_crtc->pipe; in ironlake_crtc_enable()
4899 if (WARN_ON(intel_crtc->active)) in ironlake_crtc_enable()
4902 if (intel_crtc->config->has_pch_encoder) in ironlake_crtc_enable()
4903 intel_prepare_shared_dpll(intel_crtc); in ironlake_crtc_enable()
4905 if (intel_crtc->config->has_dp_encoder) in ironlake_crtc_enable()
4906 intel_dp_set_m_n(intel_crtc, M1_N1); in ironlake_crtc_enable()
4908 intel_set_pipe_timings(intel_crtc); in ironlake_crtc_enable()
4910 if (intel_crtc->config->has_pch_encoder) { in ironlake_crtc_enable()
4911 intel_cpu_transcoder_set_m_n(intel_crtc, in ironlake_crtc_enable()
4912 &intel_crtc->config->fdi_m_n, NULL); in ironlake_crtc_enable()
4917 intel_crtc->active = true; in ironlake_crtc_enable()
4926 if (intel_crtc->config->has_pch_encoder) { in ironlake_crtc_enable()
4930 ironlake_fdi_pll_enable(intel_crtc); in ironlake_crtc_enable()
4936 ironlake_pfit_enable(intel_crtc); in ironlake_crtc_enable()
4945 intel_enable_pipe(intel_crtc); in ironlake_crtc_enable()
4947 if (intel_crtc->config->has_pch_encoder) in ironlake_crtc_enable()
4957 cpt_verify_modeset(dev, intel_crtc->pipe); in ironlake_crtc_enable()
4961 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) in hsw_crtc_supports_ips()
4970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in haswell_crtc_enable() local
4972 int pipe = intel_crtc->pipe, hsw_workaround_pipe; in haswell_crtc_enable()
4975 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); in haswell_crtc_enable()
4977 if (WARN_ON(intel_crtc->active)) in haswell_crtc_enable()
4980 if (intel_crtc_to_shared_dpll(intel_crtc)) in haswell_crtc_enable()
4981 intel_enable_shared_dpll(intel_crtc); in haswell_crtc_enable()
4983 if (intel_crtc->config->has_dp_encoder) in haswell_crtc_enable()
4984 intel_dp_set_m_n(intel_crtc, M1_N1); in haswell_crtc_enable()
4986 intel_set_pipe_timings(intel_crtc); in haswell_crtc_enable()
4988 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { in haswell_crtc_enable()
4989 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), in haswell_crtc_enable()
4990 intel_crtc->config->pixel_multiplier - 1); in haswell_crtc_enable()
4993 if (intel_crtc->config->has_pch_encoder) { in haswell_crtc_enable()
4994 intel_cpu_transcoder_set_m_n(intel_crtc, in haswell_crtc_enable()
4995 &intel_crtc->config->fdi_m_n, NULL); in haswell_crtc_enable()
5002 intel_crtc->active = true; in haswell_crtc_enable()
5012 if (intel_crtc->config->has_pch_encoder) { in haswell_crtc_enable()
5019 intel_ddi_enable_pipe_clock(intel_crtc); in haswell_crtc_enable()
5022 skylake_pfit_enable(intel_crtc); in haswell_crtc_enable()
5024 ironlake_pfit_enable(intel_crtc); in haswell_crtc_enable()
5037 intel_enable_pipe(intel_crtc); in haswell_crtc_enable()
5039 if (intel_crtc->config->has_pch_encoder) in haswell_crtc_enable()
5042 if (intel_crtc->config->dp_encoder_is_mst && !is_dsi) in haswell_crtc_enable()
5062 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) in ironlake_pfit_disable()
5081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_crtc_disable() local
5083 int pipe = intel_crtc->pipe; in ironlake_crtc_disable()
5092 if (intel_crtc->config->has_pch_encoder) in ironlake_crtc_disable()
5095 intel_disable_pipe(intel_crtc); in ironlake_crtc_disable()
5097 ironlake_pfit_disable(intel_crtc, false); in ironlake_crtc_disable()
5099 if (intel_crtc->config->has_pch_encoder) in ironlake_crtc_disable()
5106 if (intel_crtc->config->has_pch_encoder) { in ironlake_crtc_disable()
5124 ironlake_fdi_pll_disable(intel_crtc); in ironlake_crtc_disable()
5132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in haswell_crtc_disable() local
5134 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; in haswell_crtc_disable()
5135 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); in haswell_crtc_disable()
5145 if (intel_crtc->config->has_pch_encoder) in haswell_crtc_disable()
5148 intel_disable_pipe(intel_crtc); in haswell_crtc_disable()
5150 if (intel_crtc->config->dp_encoder_is_mst) in haswell_crtc_disable()
5157 skylake_scaler_disable(intel_crtc); in haswell_crtc_disable()
5159 ironlake_pfit_disable(intel_crtc, false); in haswell_crtc_disable()
5162 intel_ddi_disable_pipe_clock(intel_crtc); in haswell_crtc_disable()
5164 if (intel_crtc->config->has_pch_encoder) { in haswell_crtc_disable()
5174 static void i9xx_pfit_enable(struct intel_crtc *crtc) in i9xx_pfit_enable()
5302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in get_crtc_power_domains() local
5303 enum pipe pipe = intel_crtc->pipe; in get_crtc_power_domains()
5314 if (intel_crtc->config->pch_pfit.enabled || in get_crtc_power_domains()
5315 intel_crtc->config->pch_pfit.force_thru) in get_crtc_power_domains()
5327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in modeset_get_crtc_power_domains() local
5331 old_domains = intel_crtc->enabled_power_domains; in modeset_get_crtc_power_domains()
5332 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc); in modeset_get_crtc_power_domains()
6023 struct intel_crtc *intel_crtc; in intel_mode_max_pixclk() local
6027 for_each_intel_crtc(dev, intel_crtc) { in intel_mode_max_pixclk()
6028 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); in intel_mode_max_pixclk()
6139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in valleyview_crtc_enable() local
6141 int pipe = intel_crtc->pipe; in valleyview_crtc_enable()
6144 if (WARN_ON(intel_crtc->active)) in valleyview_crtc_enable()
6147 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); in valleyview_crtc_enable()
6149 if (intel_crtc->config->has_dp_encoder) in valleyview_crtc_enable()
6150 intel_dp_set_m_n(intel_crtc, M1_N1); in valleyview_crtc_enable()
6152 intel_set_pipe_timings(intel_crtc); in valleyview_crtc_enable()
6161 i9xx_set_pipeconf(intel_crtc); in valleyview_crtc_enable()
6163 intel_crtc->active = true; in valleyview_crtc_enable()
6173 chv_prepare_pll(intel_crtc, intel_crtc->config); in valleyview_crtc_enable()
6174 chv_enable_pll(intel_crtc, intel_crtc->config); in valleyview_crtc_enable()
6176 vlv_prepare_pll(intel_crtc, intel_crtc->config); in valleyview_crtc_enable()
6177 vlv_enable_pll(intel_crtc, intel_crtc->config); in valleyview_crtc_enable()
6185 i9xx_pfit_enable(intel_crtc); in valleyview_crtc_enable()
6189 intel_enable_pipe(intel_crtc); in valleyview_crtc_enable()
6198 static void i9xx_set_pll_dividers(struct intel_crtc *crtc) in i9xx_set_pll_dividers()
6211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i9xx_crtc_enable() local
6213 int pipe = intel_crtc->pipe; in i9xx_crtc_enable()
6215 if (WARN_ON(intel_crtc->active)) in i9xx_crtc_enable()
6218 i9xx_set_pll_dividers(intel_crtc); in i9xx_crtc_enable()
6220 if (intel_crtc->config->has_dp_encoder) in i9xx_crtc_enable()
6221 intel_dp_set_m_n(intel_crtc, M1_N1); in i9xx_crtc_enable()
6223 intel_set_pipe_timings(intel_crtc); in i9xx_crtc_enable()
6225 i9xx_set_pipeconf(intel_crtc); in i9xx_crtc_enable()
6227 intel_crtc->active = true; in i9xx_crtc_enable()
6236 i9xx_enable_pll(intel_crtc); in i9xx_crtc_enable()
6238 i9xx_pfit_enable(intel_crtc); in i9xx_crtc_enable()
6243 intel_enable_pipe(intel_crtc); in i9xx_crtc_enable()
6252 static void i9xx_pfit_disable(struct intel_crtc *crtc) in i9xx_pfit_disable()
6271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i9xx_crtc_disable() local
6273 int pipe = intel_crtc->pipe; in i9xx_crtc_disable()
6289 intel_disable_pipe(intel_crtc); in i9xx_crtc_disable()
6291 i9xx_pfit_disable(intel_crtc); in i9xx_crtc_disable()
6297 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { in i9xx_crtc_disable()
6303 i9xx_disable_pll(intel_crtc); in i9xx_crtc_disable()
6316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_disable_noatomic() local
6321 if (!intel_crtc->active) in intel_crtc_disable_noatomic()
6333 intel_crtc->active = false; in intel_crtc_disable_noatomic()
6335 intel_disable_shared_dpll(intel_crtc); in intel_crtc_disable_noatomic()
6337 domains = intel_crtc->enabled_power_domains; in intel_crtc_disable_noatomic()
6340 intel_crtc->enabled_power_domains = 0; in intel_crtc_disable_noatomic()
6499 struct intel_crtc *other_crtc; in ironlake_check_fdi_lanes()
6567 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, in ironlake_fdi_compute_config() argument
6570 struct drm_device *dev = intel_crtc->base.dev; in ironlake_fdi_compute_config()
6595 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, in ironlake_fdi_compute_config()
6596 intel_crtc->pipe, pipe_config); in ironlake_fdi_compute_config()
6634 static void hsw_compute_ips_config(struct intel_crtc *crtc, in hsw_compute_ips_config()
6645 static int intel_crtc_compute_config(struct intel_crtc *crtc, in intel_crtc_compute_config()
7172 static void i9xx_update_pll_dividers(struct intel_crtc *crtc, in i9xx_update_pll_dividers()
7230 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, in intel_pch_transcoder_set_m_n()
7243 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, in intel_cpu_transcoder_set_m_n()
7277 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) in intel_dp_set_m_n()
7302 static void vlv_compute_dpll(struct intel_crtc *crtc, in vlv_compute_dpll()
7325 static void vlv_prepare_pll(struct intel_crtc *crtc, in vlv_prepare_pll()
7416 static void chv_compute_dpll(struct intel_crtc *crtc, in chv_compute_dpll()
7429 static void chv_prepare_pll(struct intel_crtc *crtc, in chv_prepare_pll()
7546 struct intel_crtc *crtc = in vlv_force_pll_on()
7581 static void i9xx_compute_dpll(struct intel_crtc *crtc, in i9xx_compute_dpll()
7658 static void i8xx_compute_dpll(struct intel_crtc *crtc, in i8xx_compute_dpll()
7696 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) in intel_set_pipe_timings() argument
7698 struct drm_device *dev = intel_crtc->base.dev; in intel_set_pipe_timings()
7700 enum pipe pipe = intel_crtc->pipe; in intel_set_pipe_timings()
7701 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; in intel_set_pipe_timings()
7702 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; in intel_set_pipe_timings()
7716 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) in intel_set_pipe_timings()
7760 ((intel_crtc->config->pipe_src_w - 1) << 16) | in intel_set_pipe_timings()
7761 (intel_crtc->config->pipe_src_h - 1)); in intel_set_pipe_timings()
7764 static void intel_get_pipe_timings(struct intel_crtc *crtc, in intel_get_pipe_timings()
7830 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) in i9xx_set_pipeconf() argument
7832 struct drm_device *dev = intel_crtc->base.dev; in i9xx_set_pipeconf()
7838 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in i9xx_set_pipeconf()
7839 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in i9xx_set_pipeconf()
7840 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; in i9xx_set_pipeconf()
7842 if (intel_crtc->config->double_wide) in i9xx_set_pipeconf()
7848 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) in i9xx_set_pipeconf()
7852 switch (intel_crtc->config->pipe_bpp) { in i9xx_set_pipeconf()
7869 if (intel_crtc->lowfreq_avail) { in i9xx_set_pipeconf()
7877 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { in i9xx_set_pipeconf()
7879 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) in i9xx_set_pipeconf()
7886 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) in i9xx_set_pipeconf()
7889 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); in i9xx_set_pipeconf()
7890 POSTING_READ(PIPECONF(intel_crtc->pipe)); in i9xx_set_pipeconf()
7893 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, in i9xx_crtc_compute_clock()
7973 static void i9xx_get_pfit_config(struct intel_crtc *crtc, in i9xx_get_pfit_config()
8003 static void vlv_crtc_clock_get(struct intel_crtc *crtc, in vlv_crtc_clock_get()
8031 i9xx_get_initial_plane_config(struct intel_crtc *crtc, in i9xx_get_initial_plane_config()
8099 static void chv_crtc_clock_get(struct intel_crtc *crtc, in chv_crtc_clock_get()
8129 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, in i9xx_get_pipe_config()
8614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_set_pipeconf() local
8615 int pipe = intel_crtc->pipe; in ironlake_set_pipeconf()
8620 switch (intel_crtc->config->pipe_bpp) { in ironlake_set_pipeconf()
8638 if (intel_crtc->config->dither) in ironlake_set_pipeconf()
8641 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) in ironlake_set_pipeconf()
8646 if (intel_crtc->config->limited_color_range) in ironlake_set_pipeconf()
8664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_set_pipe_csc() local
8665 int pipe = intel_crtc->pipe; in intel_set_pipe_csc()
8675 if (intel_crtc->config->limited_color_range) in intel_set_pipe_csc()
8699 if (intel_crtc->config->limited_color_range) in intel_set_pipe_csc()
8710 if (intel_crtc->config->limited_color_range) in intel_set_pipe_csc()
8721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in haswell_set_pipeconf() local
8722 enum pipe pipe = intel_crtc->pipe; in haswell_set_pipeconf()
8723 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; in haswell_set_pipeconf()
8728 if (IS_HASWELL(dev) && intel_crtc->config->dither) in haswell_set_pipeconf()
8731 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) in haswell_set_pipeconf()
8739 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); in haswell_set_pipeconf()
8740 POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); in haswell_set_pipeconf()
8745 switch (intel_crtc->config->pipe_bpp) { in haswell_set_pipeconf()
8763 if (intel_crtc->config->dither) in haswell_set_pipeconf()
8815 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, in ironlake_compute_dpll() argument
8820 struct drm_crtc *crtc = &intel_crtc->base; in ironlake_compute_dpll()
8911 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, in ironlake_crtc_compute_clock()
8977 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, in intel_pch_transcoder_get_m_n()
8993 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, in intel_cpu_transcoder_get_m_n()
9035 void intel_dp_get_m_n(struct intel_crtc *crtc, in intel_dp_get_m_n()
9046 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, in ironlake_get_fdi_m_n_config()
9053 static void skylake_get_pfit_config(struct intel_crtc *crtc, in skylake_get_pfit_config()
9084 skylake_get_initial_plane_config(struct intel_crtc *crtc, in skylake_get_initial_plane_config()
9167 static void ironlake_get_pfit_config(struct intel_crtc *crtc, in ironlake_get_pfit_config()
9192 ironlake_get_initial_plane_config(struct intel_crtc *crtc, in ironlake_get_initial_plane_config()
9260 static bool ironlake_get_pipe_config(struct intel_crtc *crtc, in ironlake_get_pipe_config()
9345 struct intel_crtc *crtc; in assert_can_disable_lcpll()
9576 struct intel_crtc *intel_crtc; in ilk_max_pixel_rate() local
9580 for_each_intel_crtc(state->dev, intel_crtc) { in ilk_max_pixel_rate()
9583 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); in ilk_max_pixel_rate()
9721 static int haswell_crtc_compute_clock(struct intel_crtc *crtc, in haswell_crtc_compute_clock()
9803 static void haswell_get_ddi_port_state(struct intel_crtc *crtc, in haswell_get_ddi_port_state()
9847 static bool haswell_get_pipe_config(struct intel_crtc *crtc, in haswell_get_pipe_config()
9932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i845_update_cursor() local
9936 unsigned int width = intel_crtc->base.cursor->state->crtc_w; in i845_update_cursor()
9937 unsigned int height = intel_crtc->base.cursor->state->crtc_h; in i845_update_cursor()
9961 if (intel_crtc->cursor_cntl != 0 && in i845_update_cursor()
9962 (intel_crtc->cursor_base != base || in i845_update_cursor()
9963 intel_crtc->cursor_size != size || in i845_update_cursor()
9964 intel_crtc->cursor_cntl != cntl)) { in i845_update_cursor()
9970 intel_crtc->cursor_cntl = 0; in i845_update_cursor()
9973 if (intel_crtc->cursor_base != base) { in i845_update_cursor()
9975 intel_crtc->cursor_base = base; in i845_update_cursor()
9978 if (intel_crtc->cursor_size != size) { in i845_update_cursor()
9980 intel_crtc->cursor_size = size; in i845_update_cursor()
9983 if (intel_crtc->cursor_cntl != cntl) { in i845_update_cursor()
9986 intel_crtc->cursor_cntl = cntl; in i845_update_cursor()
9994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i9xx_update_cursor() local
9995 int pipe = intel_crtc->pipe; in i9xx_update_cursor()
10000 switch (intel_crtc->base.cursor->state->crtc_w) { in i9xx_update_cursor()
10011 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); in i9xx_update_cursor()
10023 if (intel_crtc->cursor_cntl != cntl) { in i9xx_update_cursor()
10026 intel_crtc->cursor_cntl = cntl; in i9xx_update_cursor()
10033 intel_crtc->cursor_base = base; in i9xx_update_cursor()
10042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_update_cursor() local
10043 int pipe = intel_crtc->pipe; in intel_crtc_update_cursor()
10049 base = intel_crtc->cursor_addr; in intel_crtc_update_cursor()
10051 if (x >= intel_crtc->config->pipe_src_w) in intel_crtc_update_cursor()
10054 if (y >= intel_crtc->config->pipe_src_h) in intel_crtc_update_cursor()
10131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_gamma_set() local
10134 intel_crtc->lut_r[i] = red[i] >> 8; in intel_crtc_gamma_set()
10135 intel_crtc->lut_g[i] = green[i] >> 8; in intel_crtc_gamma_set()
10136 intel_crtc->lut_b[i] = blue[i] >> 8; in intel_crtc_gamma_set()
10299 struct intel_crtc *intel_crtc; in intel_get_load_detect_pipe() local
10380 intel_crtc = to_intel_crtc(crtc); in intel_get_load_detect_pipe()
10400 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); in intel_get_load_detect_pipe()
10445 intel_wait_for_vblank(dev, intel_crtc->pipe); in intel_get_load_detect_pipe()
10469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_release_load_detect_pipe() local
10490 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); in intel_release_load_detect_pipe()
10543 static void i9xx_crtc_clock_get(struct intel_crtc *crtc, in i9xx_crtc_clock_get()
10651 static void ironlake_pch_clock_get(struct intel_crtc *crtc, in ironlake_pch_clock_get()
10675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_mode_get() local
10676 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; in intel_crtc_mode_get()
10683 enum pipe pipe = intel_crtc->pipe; in intel_crtc_mode_get()
10701 i9xx_crtc_clock_get(intel_crtc, &pipe_config); in intel_crtc_mode_get()
10749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_destroy() local
10754 work = intel_crtc->unpin_work; in intel_crtc_destroy()
10755 intel_crtc->unpin_work = NULL; in intel_crtc_destroy()
10765 kfree(intel_crtc); in intel_crtc_destroy()
10772 struct intel_crtc *crtc = to_intel_crtc(work->crtc); in intel_unpin_work_fn()
10796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in do_intel_finish_page_flip() local
10801 if (intel_crtc == NULL) in do_intel_finish_page_flip()
10809 work = intel_crtc->unpin_work; in do_intel_finish_page_flip()
10819 page_flip_completed(intel_crtc); in do_intel_finish_page_flip()
10846 static bool page_flip_finished(struct intel_crtc *crtc) in page_flip_finished()
10889 struct intel_crtc *intel_crtc = in intel_prepare_page_flip() local
10903 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) in intel_prepare_page_flip()
10904 atomic_inc_not_zero(&intel_crtc->unpin_work->pending); in intel_prepare_page_flip()
10925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen2_queue_flip() local
10936 if (intel_crtc->plane) in intel_gen2_queue_flip()
10943 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); in intel_gen2_queue_flip()
10945 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); in intel_gen2_queue_flip()
10948 intel_mark_page_flip_active(intel_crtc->unpin_work); in intel_gen2_queue_flip()
10960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen3_queue_flip() local
10968 if (intel_crtc->plane) in intel_gen3_queue_flip()
10975 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); in intel_gen3_queue_flip()
10977 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); in intel_gen3_queue_flip()
10980 intel_mark_page_flip_active(intel_crtc->unpin_work); in intel_gen3_queue_flip()
10993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen4_queue_flip() local
11006 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); in intel_gen4_queue_flip()
11008 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | in intel_gen4_queue_flip()
11016 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; in intel_gen4_queue_flip()
11019 intel_mark_page_flip_active(intel_crtc->unpin_work); in intel_gen4_queue_flip()
11032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen6_queue_flip() local
11041 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); in intel_gen6_queue_flip()
11043 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); in intel_gen6_queue_flip()
11052 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; in intel_gen6_queue_flip()
11055 intel_mark_page_flip_active(intel_crtc->unpin_work); in intel_gen6_queue_flip()
11067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen7_queue_flip() local
11071 switch (intel_crtc->plane) { in intel_gen7_queue_flip()
11147 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); in intel_gen7_queue_flip()
11150 intel_mark_page_flip_active(intel_crtc->unpin_work); in intel_gen7_queue_flip()
11181 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, in skl_do_mmio_flip() argument
11184 struct drm_device *dev = intel_crtc->base.dev; in skl_do_mmio_flip()
11186 struct drm_framebuffer *fb = intel_crtc->base.primary->fb; in skl_do_mmio_flip()
11187 const enum pipe pipe = intel_crtc->pipe; in skl_do_mmio_flip()
11227 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, in ilk_do_mmio_flip() argument
11230 struct drm_device *dev = intel_crtc->base.dev; in ilk_do_mmio_flip()
11233 to_intel_framebuffer(intel_crtc->base.primary->fb); in ilk_do_mmio_flip()
11238 reg = DSPCNTR(intel_crtc->plane); in ilk_do_mmio_flip()
11248 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); in ilk_do_mmio_flip()
11249 POSTING_READ(DSPSURF(intel_crtc->plane)); in ilk_do_mmio_flip()
11258 struct intel_crtc *crtc = mmio_flip->crtc; in intel_do_mmio_flip()
11334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in __intel_pageflip_stall_check() local
11335 struct intel_unpin_work *work = intel_crtc->unpin_work; in __intel_pageflip_stall_check()
11361 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); in __intel_pageflip_stall_check()
11363 addr = I915_READ(DSPADDR(intel_crtc->plane)); in __intel_pageflip_stall_check()
11376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_check_page_flip() local
11385 work = intel_crtc->unpin_work; in intel_check_page_flip()
11389 page_flip_completed(intel_crtc); in intel_check_page_flip()
11407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_page_flip() local
11409 enum pipe pipe = intel_crtc->pipe; in intel_crtc_page_flip()
11455 if (intel_crtc->unpin_work) { in intel_crtc_page_flip()
11461 page_flip_completed(intel_crtc); in intel_crtc_page_flip()
11471 intel_crtc->unpin_work = work; in intel_crtc_page_flip()
11474 if (atomic_read(&intel_crtc->unpin_work_count) >= 2) in intel_crtc_page_flip()
11490 atomic_inc(&intel_crtc->unpin_work_count); in intel_crtc_page_flip()
11491 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); in intel_crtc_page_flip()
11526 work->gtt_offset += intel_crtc->dspaddr_offset; in intel_crtc_page_flip()
11561 intel_fbc_disable_crtc(intel_crtc); in intel_crtc_page_flip()
11565 trace_i915_flip_request(intel_crtc->plane, obj); in intel_crtc_page_flip()
11574 atomic_dec(&intel_crtc->unpin_work_count); in intel_crtc_page_flip()
11584 intel_crtc->unpin_work = NULL; in intel_crtc_page_flip()
11660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_plane_atomic_calc_changes() local
11666 int idx = intel_crtc->base.base.id, ret; in intel_plane_atomic_calc_changes()
11690 intel_crtc->atomic.disabled_planes |= 1 << i; in intel_plane_atomic_calc_changes()
11715 intel_crtc->atomic.update_wm_pre = true; in intel_plane_atomic_calc_changes()
11718 intel_crtc->atomic.disable_cxsr = true; in intel_plane_atomic_calc_changes()
11720 intel_crtc->atomic.wait_vblank = true; in intel_plane_atomic_calc_changes()
11721 intel_crtc->atomic.update_wm_post = true; in intel_plane_atomic_calc_changes()
11724 intel_crtc->atomic.update_wm_post = true; in intel_plane_atomic_calc_changes()
11728 intel_crtc->atomic.wait_vblank = true; in intel_plane_atomic_calc_changes()
11729 intel_crtc->atomic.disable_cxsr = true; in intel_plane_atomic_calc_changes()
11732 intel_crtc->atomic.update_wm_pre = true; in intel_plane_atomic_calc_changes()
11736 intel_crtc->atomic.fb_bits |= in intel_plane_atomic_calc_changes()
11741 intel_crtc->atomic.wait_for_flips = true; in intel_plane_atomic_calc_changes()
11742 intel_crtc->atomic.pre_disable_primary = turn_off; in intel_plane_atomic_calc_changes()
11743 intel_crtc->atomic.post_enable_primary = turn_on; in intel_plane_atomic_calc_changes()
11754 intel_crtc->atomic.disable_ips = true; in intel_plane_atomic_calc_changes()
11756 intel_crtc->atomic.disable_fbc = true; in intel_plane_atomic_calc_changes()
11772 dev_priv->fbc.crtc == intel_crtc && in intel_plane_atomic_calc_changes()
11774 intel_crtc->atomic.disable_fbc = true; in intel_plane_atomic_calc_changes()
11782 intel_crtc->atomic.wait_vblank = true; in intel_plane_atomic_calc_changes()
11784 intel_crtc->atomic.update_fbc |= visible || mode_changed; in intel_plane_atomic_calc_changes()
11790 intel_crtc->atomic.wait_vblank = true; in intel_plane_atomic_calc_changes()
11791 intel_crtc->atomic.update_sprite_watermarks |= in intel_plane_atomic_calc_changes()
11807 struct intel_crtc *crtc, in check_single_encoder_cloning()
11829 struct intel_crtc *crtc) in check_encoder_cloning()
11853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_atomic_check() local
11860 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { in intel_crtc_atomic_check()
11866 intel_crtc->atomic.update_wm_post = true; in intel_crtc_atomic_check()
11871 ret = dev_priv->display.crtc_compute_clock(intel_crtc, in intel_crtc_atomic_check()
11883 ret = intel_atomic_setup_scalers(dev, intel_crtc, in intel_crtc_atomic_check()
11952 compute_baseline_pipe_bpp(struct intel_crtc *crtc, in compute_baseline_pipe_bpp()
11996 static void intel_dump_pipe_config(struct intel_crtc *crtc, in intel_dump_pipe_config()
12356 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ argument
12357 list_for_each_entry((intel_crtc), \
12360 if (mask & (1 <<(intel_crtc)->pipe))
12640 struct intel_crtc *intel_crtc; in check_wm_state() local
12649 for_each_intel_crtc(dev, intel_crtc) { in check_wm_state()
12651 const enum pipe pipe = intel_crtc->pipe; in check_wm_state()
12653 if (!intel_crtc->active) in check_wm_state()
12757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in check_crtc_state() local
12774 active = dev_priv->display.get_pipe_config(intel_crtc, in check_crtc_state()
12778 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in check_crtc_state()
12779 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in check_crtc_state()
12786 I915_STATE_WARN(intel_crtc->active != crtc->state->active, in check_crtc_state()
12788 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); in check_crtc_state()
12798 I915_STATE_WARN(active && intel_crtc->pipe != pipe, in check_crtc_state()
12813 intel_dump_pipe_config(intel_crtc, pipe_config, in check_crtc_state()
12815 intel_dump_pipe_config(intel_crtc, sw_config, in check_crtc_state()
12825 struct intel_crtc *crtc; in check_shared_dpll_state()
12893 static void update_scanline_offset(struct intel_crtc *crtc) in update_scanline_offset()
12936 struct intel_crtc *intel_crtc; in intel_modeset_clear_plls() local
12948 intel_crtc = to_intel_crtc(crtc); in intel_modeset_clear_plls()
12960 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe); in intel_modeset_clear_plls()
12973 struct intel_crtc *intel_crtc; in haswell_mode_set_planes_workaround() local
12982 intel_crtc = to_intel_crtc(crtc); in haswell_mode_set_planes_workaround()
12992 first_pipe = intel_crtc->pipe; in haswell_mode_set_planes_workaround()
13001 for_each_intel_crtc(state->dev, intel_crtc) { in haswell_mode_set_planes_workaround()
13004 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); in haswell_mode_set_planes_workaround()
13018 enabled_pipe = intel_crtc->pipe; in haswell_mode_set_planes_workaround()
13218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_atomic_commit() local
13224 intel_pre_plane_update(intel_crtc); in intel_atomic_commit()
13229 intel_crtc->active = false; in intel_atomic_commit()
13230 intel_disable_shared_dpll(intel_crtc); in intel_atomic_commit()
13247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_atomic_commit() local
13266 intel_pre_plane_update(intel_crtc); in intel_atomic_commit()
13273 intel_post_plane_update(intel_crtc); in intel_atomic_commit()
13388 struct intel_crtc *crtc; in ibx_pch_dpll_disable()
13510 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) in skl_max_scale() argument
13517 if (!intel_crtc || !crtc_state) in skl_max_scale()
13520 dev = intel_crtc->base.dev; in skl_max_scale()
13574 struct intel_crtc *intel_crtc; in intel_commit_primary_plane() local
13578 intel_crtc = to_intel_crtc(crtc); in intel_commit_primary_plane()
13606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_begin_crtc_commit() local
13611 if (intel_crtc->atomic.update_wm_pre) in intel_begin_crtc_commit()
13616 intel_pipe_update_start(intel_crtc); in intel_begin_crtc_commit()
13622 intel_update_pipe_config(intel_crtc, old_intel_state); in intel_begin_crtc_commit()
13624 skl_detach_scalers(intel_crtc); in intel_begin_crtc_commit()
13630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_finish_crtc_commit() local
13633 intel_pipe_update_end(intel_crtc); in intel_finish_crtc_commit()
13812 struct intel_crtc *intel_crtc; in intel_commit_cursor_plane() local
13817 intel_crtc = to_intel_crtc(crtc); in intel_commit_cursor_plane()
13826 intel_crtc->cursor_addr = addr; in intel_commit_cursor_plane()
13884 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, in skl_init_scalers() argument
13891 for (i = 0; i < intel_crtc->num_scalers; i++) { in skl_init_scalers()
13903 struct intel_crtc *intel_crtc; in intel_crtc_init() local
13909 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); in intel_crtc_init()
13910 if (intel_crtc == NULL) in intel_crtc_init()
13916 intel_crtc->config = crtc_state; in intel_crtc_init()
13917 intel_crtc->base.state = &crtc_state->base; in intel_crtc_init()
13918 crtc_state->base.crtc = &intel_crtc->base; in intel_crtc_init()
13923 intel_crtc->num_scalers = 1; in intel_crtc_init()
13925 intel_crtc->num_scalers = SKL_NUM_SCALERS; in intel_crtc_init()
13927 skl_init_scalers(dev, intel_crtc, crtc_state); in intel_crtc_init()
13938 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, in intel_crtc_init()
13943 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); in intel_crtc_init()
13945 intel_crtc->lut_r[i] = i; in intel_crtc_init()
13946 intel_crtc->lut_g[i] = i; in intel_crtc_init()
13947 intel_crtc->lut_b[i] = i; in intel_crtc_init()
13954 intel_crtc->pipe = pipe; in intel_crtc_init()
13955 intel_crtc->plane = pipe; in intel_crtc_init()
13958 intel_crtc->plane = !pipe; in intel_crtc_init()
13961 intel_crtc->cursor_base = ~0; in intel_crtc_init()
13962 intel_crtc->cursor_cntl = ~0; in intel_crtc_init()
13963 intel_crtc->cursor_size = ~0; in intel_crtc_init()
13965 intel_crtc->wm.cxsr_allowed = true; in intel_crtc_init()
13968 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); in intel_crtc_init()
13969 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; in intel_crtc_init()
13970 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; in intel_crtc_init()
13972 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); in intel_crtc_init()
13974 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); in intel_crtc_init()
13983 kfree(intel_crtc); in intel_crtc_init()
14004 struct intel_crtc *crtc; in intel_get_pipe_from_crtc_id()
14879 struct intel_crtc *crtc; in intel_modeset_init()
15024 intel_check_plane_mapping(struct intel_crtc *crtc) in intel_check_plane_mapping()
15042 static bool intel_crtc_has_encoders(struct intel_crtc *crtc) in intel_crtc_has_encoders()
15053 static void intel_sanitize_crtc(struct intel_crtc *crtc) in intel_sanitize_crtc()
15247 static void readout_plane_state(struct intel_crtc *crtc) in readout_plane_state()
15264 struct intel_crtc *crtc; in intel_modeset_readout_hw_state()
15382 struct intel_crtc *crtc; in intel_modeset_setup_hw_state()
15814 struct intel_crtc *crtc; in intel_modeset_preclose()