7803 	pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;  in intel_get_pipe_timings()
7809 	mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;  in intel_mode_from_pipe_config()
10201 	u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);  in intel_framebuffer_size_for_mode()
10218 	mode_cmd.width = mode->hdisplay;  in intel_framebuffer_create_for_mode()
10246 	if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,  in mode_fits_in_fbdev()
10266 	int hdisplay, vdisplay;  in intel_modeset_setup_plane_state()  local
10274 		drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);  in intel_modeset_setup_plane_state()
10276 		hdisplay = vdisplay = 0;  in intel_modeset_setup_plane_state()
10284 	plane_state->crtc_w = hdisplay;  in intel_modeset_setup_plane_state()
10288 	plane_state->src_w = hdisplay << 16;  in intel_modeset_setup_plane_state()
10704 	mode->hdisplay = (htot & 0xffff) + 1;  in intel_crtc_mode_get()