7439 	u32 dpio_val;  in chv_prepare_pll()  local
7449 	dpio_val = 0;  in chv_prepare_pll()
7479 	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));  in chv_prepare_pll()
7480 	dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);  in chv_prepare_pll()
7481 	dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);  in chv_prepare_pll()
7483 		dpio_val |= DPIO_CHV_FRAC_DIV_EN;  in chv_prepare_pll()
7484 	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);  in chv_prepare_pll()
7487 	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));  in chv_prepare_pll()
7488 	dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |  in chv_prepare_pll()
7490 	dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);  in chv_prepare_pll()
7492 		dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;  in chv_prepare_pll()
7493 	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);  in chv_prepare_pll()
7520 	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));  in chv_prepare_pll()
7521 	dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;  in chv_prepare_pll()
7522 	dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);  in chv_prepare_pll()
7523 	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);  in chv_prepare_pll()