Lines Matching refs:dev_priv
137 static int valleyview_get_vco(struct drm_i915_private *dev_priv) in valleyview_get_vco() argument
142 mutex_lock(&dev_priv->sb_lock); in valleyview_get_vco()
143 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & in valleyview_get_vco()
145 mutex_unlock(&dev_priv->sb_lock); in valleyview_get_vco()
150 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, in vlv_get_cck_clock_hpll() argument
156 if (dev_priv->hpll_freq == 0) in vlv_get_cck_clock_hpll()
157 dev_priv->hpll_freq = valleyview_get_vco(dev_priv); in vlv_get_cck_clock_hpll()
159 mutex_lock(&dev_priv->sb_lock); in vlv_get_cck_clock_hpll()
160 val = vlv_cck_read(dev_priv, reg); in vlv_get_cck_clock_hpll()
161 mutex_unlock(&dev_priv->sb_lock); in vlv_get_cck_clock_hpll()
169 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); in vlv_get_cck_clock_hpll()
175 struct drm_i915_private *dev_priv = dev->dev_private; in intel_pch_rawclk() local
185 struct drm_i915_private *dev_priv = dev->dev_private; in intel_hrawclk() local
215 static void intel_update_czclk(struct drm_i915_private *dev_priv) in intel_update_czclk() argument
217 if (!IS_VALLEYVIEW(dev_priv)) in intel_update_czclk()
220 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", in intel_update_czclk()
223 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); in intel_update_czclk()
230 struct drm_i915_private *dev_priv = dev->dev_private; in intel_fdi_link_freq() local
1087 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, in intel_pipe_to_cpu_transcoder() argument
1090 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in intel_pipe_to_cpu_transcoder()
1098 struct drm_i915_private *dev_priv = dev->dev_private; in pipe_dsl_stopped() local
1134 struct drm_i915_private *dev_priv = dev->dev_private; in intel_wait_for_pipe_off() local
1158 void assert_pll(struct drm_i915_private *dev_priv, in assert_pll() argument
1172 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) in assert_dsi_pll() argument
1177 mutex_lock(&dev_priv->sb_lock); in assert_dsi_pll()
1178 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); in assert_dsi_pll()
1179 mutex_unlock(&dev_priv->sb_lock); in assert_dsi_pll()
1192 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; in intel_crtc_to_shared_dpll() local
1197 return &dev_priv->shared_dplls[crtc->config->shared_dpll]; in intel_crtc_to_shared_dpll()
1201 void assert_shared_dpll(struct drm_i915_private *dev_priv, in assert_shared_dpll() argument
1212 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); in assert_shared_dpll()
1218 static void assert_fdi_tx(struct drm_i915_private *dev_priv, in assert_fdi_tx() argument
1222 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, in assert_fdi_tx()
1225 if (HAS_DDI(dev_priv->dev)) { in assert_fdi_tx()
1240 static void assert_fdi_rx(struct drm_i915_private *dev_priv, in assert_fdi_rx() argument
1255 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, in assert_fdi_tx_pll_enabled() argument
1261 if (INTEL_INFO(dev_priv->dev)->gen == 5) in assert_fdi_tx_pll_enabled()
1265 if (HAS_DDI(dev_priv->dev)) in assert_fdi_tx_pll_enabled()
1272 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, in assert_fdi_rx_pll() argument
1285 void assert_panel_unlocked(struct drm_i915_private *dev_priv, in assert_panel_unlocked() argument
1288 struct drm_device *dev = dev_priv->dev; in assert_panel_unlocked()
1327 static void assert_cursor(struct drm_i915_private *dev_priv, in assert_cursor() argument
1330 struct drm_device *dev = dev_priv->dev; in assert_cursor()
1345 void assert_pipe(struct drm_i915_private *dev_priv, in assert_pipe() argument
1349 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, in assert_pipe()
1353 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in assert_pipe()
1354 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in assert_pipe()
1357 if (!intel_display_power_is_enabled(dev_priv, in assert_pipe()
1370 static void assert_plane(struct drm_i915_private *dev_priv, in assert_plane() argument
1386 static void assert_planes_disabled(struct drm_i915_private *dev_priv, in assert_planes_disabled() argument
1389 struct drm_device *dev = dev_priv->dev; in assert_planes_disabled()
1402 for_each_pipe(dev_priv, i) { in assert_planes_disabled()
1412 static void assert_sprites_disabled(struct drm_i915_private *dev_priv, in assert_sprites_disabled() argument
1415 struct drm_device *dev = dev_priv->dev; in assert_sprites_disabled()
1419 for_each_sprite(dev_priv, pipe, sprite) { in assert_sprites_disabled()
1426 for_each_sprite(dev_priv, pipe, sprite) { in assert_sprites_disabled()
1451 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) in ibx_assert_pch_refclk_enabled() argument
1456 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); in ibx_assert_pch_refclk_enabled()
1464 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, in assert_pch_transcoder_disabled() argument
1477 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, in dp_pipe_enabled() argument
1483 if (HAS_PCH_CPT(dev_priv->dev)) { in dp_pipe_enabled()
1488 } else if (IS_CHERRYVIEW(dev_priv->dev)) { in dp_pipe_enabled()
1498 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, in hdmi_pipe_enabled() argument
1504 if (HAS_PCH_CPT(dev_priv->dev)) { in hdmi_pipe_enabled()
1507 } else if (IS_CHERRYVIEW(dev_priv->dev)) { in hdmi_pipe_enabled()
1517 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, in lvds_pipe_enabled() argument
1523 if (HAS_PCH_CPT(dev_priv->dev)) { in lvds_pipe_enabled()
1533 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, in adpa_pipe_enabled() argument
1538 if (HAS_PCH_CPT(dev_priv->dev)) { in adpa_pipe_enabled()
1548 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, in assert_pch_dp_disabled() argument
1552 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), in assert_pch_dp_disabled()
1556 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 in assert_pch_dp_disabled()
1561 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, in assert_pch_hdmi_disabled() argument
1565 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), in assert_pch_hdmi_disabled()
1569 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 in assert_pch_hdmi_disabled()
1574 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, in assert_pch_ports_disabled() argument
1579 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); in assert_pch_ports_disabled()
1580 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); in assert_pch_ports_disabled()
1581 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); in assert_pch_ports_disabled()
1584 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), in assert_pch_ports_disabled()
1589 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), in assert_pch_ports_disabled()
1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); in assert_pch_ports_disabled()
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); in assert_pch_ports_disabled()
1595 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); in assert_pch_ports_disabled()
1602 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_enable_pll() local
1606 assert_pipe_disabled(dev_priv, crtc->pipe); in vlv_enable_pll()
1609 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); in vlv_enable_pll()
1612 if (IS_MOBILE(dev_priv->dev)) in vlv_enable_pll()
1613 assert_panel_unlocked(dev_priv, crtc->pipe); in vlv_enable_pll()
1641 struct drm_i915_private *dev_priv = dev->dev_private; in chv_enable_pll() local
1646 assert_pipe_disabled(dev_priv, crtc->pipe); in chv_enable_pll()
1648 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); in chv_enable_pll()
1650 mutex_lock(&dev_priv->sb_lock); in chv_enable_pll()
1653 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); in chv_enable_pll()
1655 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); in chv_enable_pll()
1657 mutex_unlock(&dev_priv->sb_lock); in chv_enable_pll()
1691 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_enable_pll() local
1695 assert_pipe_disabled(dev_priv, crtc->pipe); in i9xx_enable_pll()
1702 assert_panel_unlocked(dev_priv, crtc->pipe); in i9xx_enable_pll()
1766 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_disable_pll() local
1780 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in i9xx_disable_pll()
1781 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in i9xx_disable_pll()
1785 assert_pipe_disabled(dev_priv, pipe); in i9xx_disable_pll()
1791 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) in vlv_disable_pll() argument
1796 assert_pipe_disabled(dev_priv, pipe); in vlv_disable_pll()
1810 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) in chv_disable_pll() argument
1816 assert_pipe_disabled(dev_priv, pipe); in chv_disable_pll()
1826 mutex_lock(&dev_priv->sb_lock); in chv_disable_pll()
1829 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); in chv_disable_pll()
1831 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); in chv_disable_pll()
1833 mutex_unlock(&dev_priv->sb_lock); in chv_disable_pll()
1836 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, in vlv_wait_port_ready() argument
1869 struct drm_i915_private *dev_priv = dev->dev_private; in intel_prepare_shared_dpll() local
1879 assert_shared_dpll_disabled(dev_priv, pll); in intel_prepare_shared_dpll()
1881 pll->mode_set(dev_priv, pll); in intel_prepare_shared_dpll()
1896 struct drm_i915_private *dev_priv = dev->dev_private; in intel_enable_shared_dpll() local
1911 assert_shared_dpll_enabled(dev_priv, pll); in intel_enable_shared_dpll()
1916 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); in intel_enable_shared_dpll()
1919 pll->enable(dev_priv, pll); in intel_enable_shared_dpll()
1926 struct drm_i915_private *dev_priv = dev->dev_private; in intel_disable_shared_dpll() local
1944 assert_shared_dpll_disabled(dev_priv, pll); in intel_disable_shared_dpll()
1948 assert_shared_dpll_enabled(dev_priv, pll); in intel_disable_shared_dpll()
1954 pll->disable(dev_priv, pll); in intel_disable_shared_dpll()
1957 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); in intel_disable_shared_dpll()
1960 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, in ironlake_enable_pch_transcoder() argument
1963 struct drm_device *dev = dev_priv->dev; in ironlake_enable_pch_transcoder()
1964 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in ironlake_enable_pch_transcoder()
1972 assert_shared_dpll_enabled(dev_priv, in ironlake_enable_pch_transcoder()
1976 assert_fdi_tx_enabled(dev_priv, pipe); in ironlake_enable_pch_transcoder()
1977 assert_fdi_rx_enabled(dev_priv, pipe); in ironlake_enable_pch_transcoder()
1992 if (HAS_PCH_IBX(dev_priv->dev)) { in ironlake_enable_pch_transcoder()
2007 if (HAS_PCH_IBX(dev_priv->dev) && in ironlake_enable_pch_transcoder()
2020 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, in lpt_enable_pch_transcoder() argument
2026 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); in lpt_enable_pch_transcoder()
2029 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); in lpt_enable_pch_transcoder()
2030 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); in lpt_enable_pch_transcoder()
2051 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, in ironlake_disable_pch_transcoder() argument
2054 struct drm_device *dev = dev_priv->dev; in ironlake_disable_pch_transcoder()
2058 assert_fdi_tx_disabled(dev_priv, pipe); in ironlake_disable_pch_transcoder()
2059 assert_fdi_rx_disabled(dev_priv, pipe); in ironlake_disable_pch_transcoder()
2062 assert_pch_ports_disabled(dev_priv, pipe); in ironlake_disable_pch_transcoder()
2081 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) in lpt_disable_pch_transcoder() argument
2108 struct drm_i915_private *dev_priv = dev->dev_private; in intel_enable_pipe() local
2110 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, in intel_enable_pipe()
2118 assert_planes_disabled(dev_priv, pipe); in intel_enable_pipe()
2119 assert_cursor_disabled(dev_priv, pipe); in intel_enable_pipe()
2120 assert_sprites_disabled(dev_priv, pipe); in intel_enable_pipe()
2122 if (HAS_PCH_LPT(dev_priv->dev)) in intel_enable_pipe()
2132 if (HAS_GMCH_DISPLAY(dev_priv->dev)) in intel_enable_pipe()
2134 assert_dsi_pll_enabled(dev_priv); in intel_enable_pipe()
2136 assert_pll_enabled(dev_priv, pipe); in intel_enable_pipe()
2140 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); in intel_enable_pipe()
2141 assert_fdi_tx_pll_enabled(dev_priv, in intel_enable_pipe()
2150 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in intel_enable_pipe()
2151 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); in intel_enable_pipe()
2171 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; in intel_disable_pipe() local
2183 assert_planes_disabled(dev_priv, pipe); in intel_disable_pipe()
2184 assert_cursor_disabled(dev_priv, pipe); in intel_disable_pipe()
2185 assert_sprites_disabled(dev_priv, pipe); in intel_disable_pipe()
2200 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && in intel_disable_pipe()
2201 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in intel_disable_pipe()
2317 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv) in intel_linear_alignment() argument
2319 if (INTEL_INFO(dev_priv)->gen >= 9) in intel_linear_alignment()
2321 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || in intel_linear_alignment()
2322 IS_VALLEYVIEW(dev_priv)) in intel_linear_alignment()
2324 else if (INTEL_INFO(dev_priv)->gen >= 4) in intel_linear_alignment()
2338 struct drm_i915_private *dev_priv = dev->dev_private; in intel_pin_and_fence_fb_obj() local
2348 alignment = intel_linear_alignment(dev_priv); in intel_pin_and_fence_fb_obj()
2389 intel_runtime_pm_get(dev_priv); in intel_pin_and_fence_fb_obj()
2391 dev_priv->mm.interruptible = false; in intel_pin_and_fence_fb_obj()
2421 dev_priv->mm.interruptible = true; in intel_pin_and_fence_fb_obj()
2422 intel_runtime_pm_put(dev_priv); in intel_pin_and_fence_fb_obj()
2428 dev_priv->mm.interruptible = true; in intel_pin_and_fence_fb_obj()
2429 intel_runtime_pm_put(dev_priv); in intel_pin_and_fence_fb_obj()
2453 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv, in intel_gen4_compute_page_offset() argument
2470 unsigned int alignment = intel_linear_alignment(dev_priv) - 1; in intel_gen4_compute_page_offset()
2532 struct drm_i915_private *dev_priv = to_i915(dev); in intel_alloc_initial_plane_obj() local
2548 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size) in intel_alloc_initial_plane_obj()
2605 struct drm_i915_private *dev_priv = dev->dev_private; in intel_find_initial_plane_obj() local
2676 dev_priv->preserve_bios_swizzle = true; in intel_find_initial_plane_obj()
2690 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_update_primary_plane() local
2777 intel_gen4_compute_page_offset(dev_priv, in i9xx_update_primary_plane()
2820 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_update_primary_plane() local
2882 intel_gen4_compute_page_offset(dev_priv, in ironlake_update_primary_plane()
2982 struct drm_i915_private *dev_priv = dev->dev_private; in skl_detach_scaler() local
3092 struct drm_i915_private *dev_priv = dev->dev_private; in skylake_update_primary_plane() local
3198 struct drm_i915_private *dev_priv = dev->dev_private; in intel_pipe_set_base_atomic() local
3200 if (dev_priv->fbc.disable_fbc) in intel_pipe_set_base_atomic()
3201 dev_priv->fbc.disable_fbc(dev_priv); in intel_pipe_set_base_atomic()
3203 dev_priv->display.update_primary_plane(crtc, fb, x, y); in intel_pipe_set_base_atomic()
3260 struct drm_i915_private *dev_priv = to_i915(dev); in intel_finish_reset() local
3292 intel_runtime_pm_disable_interrupts(dev_priv); in intel_finish_reset()
3293 intel_runtime_pm_enable_interrupts(dev_priv); in intel_finish_reset()
3297 spin_lock_irq(&dev_priv->irq_lock); in intel_finish_reset()
3298 if (dev_priv->display.hpd_irq_setup) in intel_finish_reset()
3299 dev_priv->display.hpd_irq_setup(dev); in intel_finish_reset()
3300 spin_unlock_irq(&dev_priv->irq_lock); in intel_finish_reset()
3304 intel_hpd_init(dev_priv); in intel_finish_reset()
3313 struct drm_i915_private *dev_priv = to_i915(obj->base.dev); in intel_finish_fb() local
3314 bool was_interruptible = dev_priv->mm.interruptible; in intel_finish_fb()
3328 dev_priv->mm.interruptible = false; in intel_finish_fb()
3330 dev_priv->mm.interruptible = was_interruptible; in intel_finish_fb()
3338 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crtc_has_pending_flip() local
3342 if (i915_reset_in_progress(&dev_priv->gpu_error) || in intel_crtc_has_pending_flip()
3343 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) in intel_crtc_has_pending_flip()
3357 struct drm_i915_private *dev_priv = dev->dev_private; in intel_update_pipe_config() local
3401 struct drm_i915_private *dev_priv = dev->dev_private; in intel_fdi_normal_train() local
3443 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_fdi_link_train() local
3449 assert_pipe_enabled(dev_priv, pipe); in ironlake_fdi_link_train()
3543 struct drm_i915_private *dev_priv = dev->dev_private; in gen6_fdi_link_train() local
3675 struct drm_i915_private *dev_priv = dev->dev_private; in ivb_manual_fdi_link_train() local
3793 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_fdi_pll_enable() local
3830 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_fdi_pll_disable() local
3859 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_fdi_disable() local
3934 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); in page_flip_completed() local
3948 wake_up_all(&dev_priv->pending_flip_queue); in page_flip_completed()
3949 queue_work(dev_priv->wq, &work->work); in page_flip_completed()
3958 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crtc_wait_for_pending_flips() local
3960 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); in intel_crtc_wait_for_pending_flips()
3961 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, in intel_crtc_wait_for_pending_flips()
3985 struct drm_i915_private *dev_priv = dev->dev_private; in lpt_program_iclkip() local
3990 mutex_lock(&dev_priv->sb_lock); in lpt_program_iclkip()
3998 intel_sbi_write(dev_priv, SBI_SSCCTL6, in lpt_program_iclkip()
3999 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | in lpt_program_iclkip()
4042 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); in lpt_program_iclkip()
4049 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); in lpt_program_iclkip()
4052 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); in lpt_program_iclkip()
4055 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); in lpt_program_iclkip()
4058 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); in lpt_program_iclkip()
4060 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); in lpt_program_iclkip()
4067 mutex_unlock(&dev_priv->sb_lock); in lpt_program_iclkip()
4074 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_pch_transcoder_set_timings() local
4096 struct drm_i915_private *dev_priv = dev->dev_private; in cpt_set_fdi_bc_bifurcation() local
4149 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_pch_enable() local
4154 assert_pch_transcoder_disabled(dev_priv, pipe); in ironlake_pch_enable()
4165 dev_priv->display.fdi_link_train(crtc); in ironlake_pch_enable()
4192 assert_panel_unlocked(dev_priv, pipe); in ironlake_pch_enable()
4230 ironlake_enable_pch_transcoder(dev_priv, pipe); in ironlake_pch_enable()
4236 struct drm_i915_private *dev_priv = dev->dev_private; in lpt_pch_enable() local
4240 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); in lpt_pch_enable()
4247 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); in lpt_pch_enable()
4253 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; in intel_get_shared_dpll() local
4257 int max = dev_priv->num_shared_dpll; in intel_get_shared_dpll()
4261 if (HAS_PCH_IBX(dev_priv->dev)) { in intel_get_shared_dpll()
4264 pll = &dev_priv->shared_dplls[i]; in intel_get_shared_dpll()
4274 if (IS_BROXTON(dev_priv->dev)) { in intel_get_shared_dpll()
4286 pll = &dev_priv->shared_dplls[i]; in intel_get_shared_dpll()
4292 } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv)) in intel_get_shared_dpll()
4297 pll = &dev_priv->shared_dplls[i]; in intel_get_shared_dpll()
4315 for (i = 0; i < dev_priv->num_shared_dpll; i++) { in intel_get_shared_dpll()
4316 pll = &dev_priv->shared_dplls[i]; in intel_get_shared_dpll()
4342 struct drm_i915_private *dev_priv = to_i915(state->dev); in intel_shared_dpll_commit() local
4351 for (i = 0; i < dev_priv->num_shared_dpll; i++) { in intel_shared_dpll_commit()
4352 pll = &dev_priv->shared_dplls[i]; in intel_shared_dpll_commit()
4359 struct drm_i915_private *dev_priv = dev->dev_private; in cpt_verify_modeset() local
4534 struct drm_i915_private *dev_priv = dev->dev_private; in skylake_pfit_enable() local
4562 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_pfit_enable() local
4583 struct drm_i915_private *dev_priv = dev->dev_private; in hsw_enable_ips() local
4591 assert_plane_enabled(dev_priv, crtc->plane); in hsw_enable_ips()
4593 mutex_lock(&dev_priv->rps.hw_lock); in hsw_enable_ips()
4594 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); in hsw_enable_ips()
4595 mutex_unlock(&dev_priv->rps.hw_lock); in hsw_enable_ips()
4616 struct drm_i915_private *dev_priv = dev->dev_private; in hsw_disable_ips() local
4621 assert_plane_enabled(dev_priv, crtc->plane); in hsw_disable_ips()
4623 mutex_lock(&dev_priv->rps.hw_lock); in hsw_disable_ips()
4624 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); in hsw_disable_ips()
4625 mutex_unlock(&dev_priv->rps.hw_lock); in hsw_disable_ips()
4642 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crtc_load_lut() local
4652 if (HAS_GMCH_DISPLAY(dev_priv->dev)) { in intel_crtc_load_lut()
4654 assert_dsi_pll_enabled(dev_priv); in intel_crtc_load_lut()
4656 assert_pll_enabled(dev_priv, pipe); in intel_crtc_load_lut()
4691 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crtc_dpms_overlay_disable() local
4694 dev_priv->mm.interruptible = false; in intel_crtc_dpms_overlay_disable()
4696 dev_priv->mm.interruptible = true; in intel_crtc_dpms_overlay_disable()
4719 struct drm_i915_private *dev_priv = dev->dev_private; in intel_post_enable_primary() local
4747 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); in intel_post_enable_primary()
4751 i9xx_check_fifo_underruns(dev_priv); in intel_post_enable_primary()
4768 struct drm_i915_private *dev_priv = dev->dev_private; in intel_pre_disable_primary() local
4779 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); in intel_pre_disable_primary()
4791 intel_set_memory_cxsr(dev_priv, false); in intel_pre_disable_primary()
4792 dev_priv->wm.vlv.cxsr = false; in intel_pre_disable_primary()
4809 struct drm_i915_private *dev_priv = dev->dev_private; in intel_post_plane_update() local
4824 intel_fbc_update(dev_priv); in intel_post_plane_update()
4839 struct drm_i915_private *dev_priv = dev->dev_private; in intel_pre_plane_update() local
4867 intel_set_memory_cxsr(dev_priv, false); in intel_pre_plane_update()
4894 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_crtc_enable() local
4919 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); in ironlake_crtc_enable()
4920 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); in ironlake_crtc_enable()
4932 assert_fdi_tx_disabled(dev_priv, pipe); in ironlake_crtc_enable()
4933 assert_fdi_rx_disabled(dev_priv, pipe); in ironlake_crtc_enable()
4969 struct drm_i915_private *dev_priv = dev->dev_private; in haswell_crtc_enable() local
5004 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); in haswell_crtc_enable()
5013 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, in haswell_crtc_enable()
5015 dev_priv->display.fdi_link_train(crtc); in haswell_crtc_enable()
5065 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_pfit_disable() local
5080 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_crtc_disable() local
5093 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); in ironlake_crtc_disable()
5107 ironlake_disable_pch_transcoder(dev_priv, pipe); in ironlake_crtc_disable()
5131 struct drm_i915_private *dev_priv = dev->dev_private; in haswell_crtc_disable() local
5146 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, in haswell_crtc_disable()
5154 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); in haswell_crtc_disable()
5165 lpt_disable_pch_transcoder(dev_priv); in haswell_crtc_disable()
5177 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_pfit_enable() local
5188 assert_pipe_disabled(dev_priv, crtc->pipe); in i9xx_pfit_enable()
5326 struct drm_i915_private *dev_priv = crtc->dev->dev_private; in modeset_get_crtc_power_domains() local
5337 intel_display_power_get(dev_priv, domain); in modeset_get_crtc_power_domains()
5342 static void modeset_put_power_domains(struct drm_i915_private *dev_priv, in modeset_put_power_domains() argument
5348 intel_display_power_put(dev_priv, domain); in modeset_put_power_domains()
5354 struct drm_i915_private *dev_priv = dev->dev_private; in modeset_update_crtc_power_domains() local
5366 if (dev_priv->display.modeset_commit_cdclk) { in modeset_update_crtc_power_domains()
5369 if (cdclk != dev_priv->cdclk_freq && in modeset_update_crtc_power_domains()
5371 dev_priv->display.modeset_commit_cdclk(state); in modeset_update_crtc_power_domains()
5376 modeset_put_power_domains(dev_priv, put_domains[i]); in modeset_update_crtc_power_domains()
5379 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) in intel_compute_max_dotclk() argument
5381 int max_cdclk_freq = dev_priv->max_cdclk_freq; in intel_compute_max_dotclk()
5383 if (INTEL_INFO(dev_priv)->gen >= 9 || in intel_compute_max_dotclk()
5384 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) in intel_compute_max_dotclk()
5386 else if (IS_CHERRYVIEW(dev_priv)) in intel_compute_max_dotclk()
5388 else if (INTEL_INFO(dev_priv)->gen < 4) in intel_compute_max_dotclk()
5396 struct drm_i915_private *dev_priv = dev->dev_private; in intel_update_max_cdclk() local
5402 dev_priv->max_cdclk_freq = 675000; in intel_update_max_cdclk()
5404 dev_priv->max_cdclk_freq = 540000; in intel_update_max_cdclk()
5406 dev_priv->max_cdclk_freq = 450000; in intel_update_max_cdclk()
5408 dev_priv->max_cdclk_freq = 337500; in intel_update_max_cdclk()
5417 dev_priv->max_cdclk_freq = 450000; in intel_update_max_cdclk()
5419 dev_priv->max_cdclk_freq = 450000; in intel_update_max_cdclk()
5421 dev_priv->max_cdclk_freq = 540000; in intel_update_max_cdclk()
5423 dev_priv->max_cdclk_freq = 675000; in intel_update_max_cdclk()
5425 dev_priv->max_cdclk_freq = 320000; in intel_update_max_cdclk()
5427 dev_priv->max_cdclk_freq = 400000; in intel_update_max_cdclk()
5430 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; in intel_update_max_cdclk()
5433 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); in intel_update_max_cdclk()
5436 dev_priv->max_cdclk_freq); in intel_update_max_cdclk()
5439 dev_priv->max_dotclk_freq); in intel_update_max_cdclk()
5444 struct drm_i915_private *dev_priv = dev->dev_private; in intel_update_cdclk() local
5446 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); in intel_update_cdclk()
5448 dev_priv->cdclk_freq); in intel_update_cdclk()
5461 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); in intel_update_cdclk()
5464 if (dev_priv->max_cdclk_freq == 0) in intel_update_cdclk()
5470 struct drm_i915_private *dev_priv = dev->dev_private; in broxton_set_cdclk() local
5512 mutex_lock(&dev_priv->rps.hw_lock); in broxton_set_cdclk()
5514 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, in broxton_set_cdclk()
5516 mutex_unlock(&dev_priv->rps.hw_lock); in broxton_set_cdclk()
5573 mutex_lock(&dev_priv->rps.hw_lock); in broxton_set_cdclk()
5574 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, in broxton_set_cdclk()
5576 mutex_unlock(&dev_priv->rps.hw_lock); in broxton_set_cdclk()
5589 struct drm_i915_private *dev_priv = dev->dev_private; in broxton_init_cdclk() local
5603 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); in broxton_init_cdclk()
5631 struct drm_i915_private *dev_priv = dev->dev_private; in broxton_uninit_cdclk() local
5644 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); in broxton_uninit_cdclk()
5680 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) in skl_dpll0_enable() argument
5730 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) in skl_cdclk_pcu_ready() argument
5737 mutex_lock(&dev_priv->rps.hw_lock); in skl_cdclk_pcu_ready()
5738 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); in skl_cdclk_pcu_ready()
5739 mutex_unlock(&dev_priv->rps.hw_lock); in skl_cdclk_pcu_ready()
5744 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) in skl_cdclk_wait_for_pcu_ready() argument
5749 if (skl_cdclk_pcu_ready(dev_priv)) in skl_cdclk_wait_for_pcu_ready()
5757 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) in skl_set_cdclk() argument
5759 struct drm_device *dev = dev_priv->dev; in skl_set_cdclk()
5764 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { in skl_set_cdclk()
5797 mutex_lock(&dev_priv->rps.hw_lock); in skl_set_cdclk()
5798 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); in skl_set_cdclk()
5799 mutex_unlock(&dev_priv->rps.hw_lock); in skl_set_cdclk()
5804 void skl_uninit_cdclk(struct drm_i915_private *dev_priv) in skl_uninit_cdclk() argument
5818 if (dev_priv->csr.dmc_payload) { in skl_uninit_cdclk()
5826 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); in skl_uninit_cdclk()
5829 void skl_init_cdclk(struct drm_i915_private *dev_priv) in skl_init_cdclk() argument
5839 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); in skl_init_cdclk()
5844 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); in skl_init_cdclk()
5845 skl_dpll0_enable(dev_priv, required_vco); in skl_init_cdclk()
5849 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); in skl_init_cdclk()
5864 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_set_cdclk() local
5867 WARN_ON(dev_priv->display.get_display_clock_speed(dev) in valleyview_set_cdclk()
5868 != dev_priv->cdclk_freq); in valleyview_set_cdclk()
5877 mutex_lock(&dev_priv->rps.hw_lock); in valleyview_set_cdclk()
5878 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); in valleyview_set_cdclk()
5881 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); in valleyview_set_cdclk()
5882 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & in valleyview_set_cdclk()
5887 mutex_unlock(&dev_priv->rps.hw_lock); in valleyview_set_cdclk()
5889 mutex_lock(&dev_priv->sb_lock); in valleyview_set_cdclk()
5894 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; in valleyview_set_cdclk()
5897 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); in valleyview_set_cdclk()
5900 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); in valleyview_set_cdclk()
5902 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & in valleyview_set_cdclk()
5909 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); in valleyview_set_cdclk()
5920 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); in valleyview_set_cdclk()
5922 mutex_unlock(&dev_priv->sb_lock); in valleyview_set_cdclk()
5929 struct drm_i915_private *dev_priv = dev->dev_private; in cherryview_set_cdclk() local
5932 WARN_ON(dev_priv->display.get_display_clock_speed(dev) in cherryview_set_cdclk()
5933 != dev_priv->cdclk_freq); in cherryview_set_cdclk()
5951 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; in cherryview_set_cdclk()
5953 mutex_lock(&dev_priv->rps.hw_lock); in cherryview_set_cdclk()
5954 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); in cherryview_set_cdclk()
5957 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); in cherryview_set_cdclk()
5958 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & in cherryview_set_cdclk()
5963 mutex_unlock(&dev_priv->rps.hw_lock); in cherryview_set_cdclk()
5968 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, in valleyview_calc_cdclk() argument
5971 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; in valleyview_calc_cdclk()
5972 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; in valleyview_calc_cdclk()
5987 if (!IS_CHERRYVIEW(dev_priv) && in valleyview_calc_cdclk()
5998 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, in broxton_calc_cdclk() argument
6045 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_modeset_calc_cdclk() local
6052 valleyview_calc_cdclk(dev_priv, max_pixclk); in valleyview_modeset_calc_cdclk()
6060 struct drm_i915_private *dev_priv = dev->dev_private; in broxton_modeset_calc_cdclk() local
6067 broxton_calc_cdclk(dev_priv, max_pixclk); in broxton_modeset_calc_cdclk()
6072 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) in vlv_program_pfi_credits() argument
6076 if (IS_CHERRYVIEW(dev_priv)) in vlv_program_pfi_credits()
6081 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
6083 if (IS_CHERRYVIEW(dev_priv)) in vlv_program_pfi_credits()
6112 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_modeset_commit_cdclk() local
6123 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); in valleyview_modeset_commit_cdclk()
6130 vlv_program_pfi_credits(dev_priv); in valleyview_modeset_commit_cdclk()
6132 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); in valleyview_modeset_commit_cdclk()
6138 struct drm_i915_private *dev_priv = to_i915(dev); in valleyview_crtc_enable() local
6155 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_crtc_enable() local
6165 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); in valleyview_crtc_enable()
6201 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_set_pll_dividers() local
6210 struct drm_i915_private *dev_priv = to_i915(dev); in i9xx_crtc_enable() local
6230 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); in i9xx_crtc_enable()
6255 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_pfit_disable() local
6260 assert_pipe_disabled(dev_priv, crtc->pipe); in i9xx_pfit_disable()
6270 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_crtc_disable() local
6299 chv_disable_pll(dev_priv, pipe); in i9xx_crtc_disable()
6301 vlv_disable_pll(dev_priv, pipe); in i9xx_crtc_disable()
6311 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); in i9xx_crtc_disable()
6317 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in intel_crtc_disable_noatomic() local
6332 dev_priv->display.crtc_disable(crtc); in intel_crtc_disable_noatomic()
6339 intel_display_power_put(dev_priv, domain); in intel_crtc_disable_noatomic()
6613 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, in pipe_config_supports_ips() argument
6620 if (IS_HASWELL(dev_priv->dev)) in pipe_config_supports_ips()
6631 dev_priv->max_cdclk_freq * 95 / 100; in pipe_config_supports_ips()
6638 struct drm_i915_private *dev_priv = dev->dev_private; in hsw_compute_ips_config() local
6642 pipe_config_supports_ips(dev_priv, pipe_config); in hsw_compute_ips_config()
6649 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crtc_compute_config() local
6654 int clock_limit = dev_priv->max_cdclk_freq; in intel_crtc_compute_config()
6701 struct drm_i915_private *dev_priv = to_i915(dev); in skylake_get_display_clock_speed() local
6748 struct drm_i915_private *dev_priv = to_i915(dev); in broxton_get_display_clock_speed() local
6776 struct drm_i915_private *dev_priv = dev->dev_private; in broadwell_get_display_clock_speed() local
6796 struct drm_i915_private *dev_priv = dev->dev_private; in haswell_get_display_clock_speed() local
6930 struct drm_i915_private *dev_priv = dev->dev_private; in intel_hpll_vco() local
7130 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) in intel_panel_use_ssc() argument
7134 return dev_priv->vbt.lvds_use_ssc in intel_panel_use_ssc()
7135 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); in intel_panel_use_ssc()
7142 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_get_refclk() local
7150 intel_panel_use_ssc(dev_priv) && num_connectors < 2) { in i9xx_get_refclk()
7151 refclk = dev_priv->vbt.lvds_ssc_freq; in i9xx_get_refclk()
7201 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe in vlv_pllb_recal_opamp() argument
7210 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); in vlv_pllb_recal_opamp()
7213 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); in vlv_pllb_recal_opamp()
7215 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); in vlv_pllb_recal_opamp()
7218 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); in vlv_pllb_recal_opamp()
7220 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); in vlv_pllb_recal_opamp()
7222 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); in vlv_pllb_recal_opamp()
7224 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); in vlv_pllb_recal_opamp()
7227 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); in vlv_pllb_recal_opamp()
7234 struct drm_i915_private *dev_priv = dev->dev_private; in intel_pch_transcoder_set_m_n() local
7248 struct drm_i915_private *dev_priv = dev->dev_private; in intel_cpu_transcoder_set_m_n() local
7329 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_prepare_pll() local
7335 mutex_lock(&dev_priv->sb_lock); in vlv_prepare_pll()
7347 vlv_pllb_recal_opamp(dev_priv, pipe); in vlv_prepare_pll()
7350 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); in vlv_prepare_pll()
7353 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); in vlv_prepare_pll()
7355 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); in vlv_prepare_pll()
7358 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); in vlv_prepare_pll()
7372 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); in vlv_prepare_pll()
7375 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); in vlv_prepare_pll()
7381 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), in vlv_prepare_pll()
7384 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), in vlv_prepare_pll()
7390 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
7393 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
7398 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
7401 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
7405 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); in vlv_prepare_pll()
7410 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); in vlv_prepare_pll()
7412 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); in vlv_prepare_pll()
7413 mutex_unlock(&dev_priv->sb_lock); in vlv_prepare_pll()
7433 struct drm_i915_private *dev_priv = dev->dev_private; in chv_prepare_pll() local
7458 mutex_lock(&dev_priv->sb_lock); in chv_prepare_pll()
7461 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), in chv_prepare_pll()
7468 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); in chv_prepare_pll()
7471 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), in chv_prepare_pll()
7476 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); in chv_prepare_pll()
7479 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); in chv_prepare_pll()
7484 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); in chv_prepare_pll()
7487 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); in chv_prepare_pll()
7493 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); in chv_prepare_pll()
7518 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); in chv_prepare_pll()
7520 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); in chv_prepare_pll()
7523 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); in chv_prepare_pll()
7526 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), in chv_prepare_pll()
7527 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | in chv_prepare_pll()
7530 mutex_unlock(&dev_priv->sb_lock); in chv_prepare_pll()
7587 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_compute_dpll() local
7643 intel_panel_use_ssc(dev_priv) && num_connectors < 2) in i9xx_compute_dpll()
7664 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_compute_dpll() local
7687 intel_panel_use_ssc(dev_priv) && num_connectors < 2) in i8xx_compute_dpll()
7699 struct drm_i915_private *dev_priv = dev->dev_private; in intel_set_pipe_timings() local
7768 struct drm_i915_private *dev_priv = dev->dev_private; in intel_get_pipe_timings() local
7833 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_set_pipeconf() local
7838 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in i9xx_set_pipeconf()
7839 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in i9xx_set_pipeconf()
7897 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_crtc_compute_clock() local
7942 ok = dev_priv->display.find_dpll(limit, crtc_state, in i9xx_crtc_compute_clock()
7977 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_get_pfit_config() local
8007 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_crtc_clock_get() local
8017 mutex_lock(&dev_priv->sb_lock); in vlv_crtc_clock_get()
8018 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); in vlv_crtc_clock_get()
8019 mutex_unlock(&dev_priv->sb_lock); in vlv_crtc_clock_get()
8035 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_get_initial_plane_config() local
8103 struct drm_i915_private *dev_priv = dev->dev_private; in chv_crtc_clock_get() local
8110 mutex_lock(&dev_priv->sb_lock); in chv_crtc_clock_get()
8111 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); in chv_crtc_clock_get()
8112 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); in chv_crtc_clock_get()
8113 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); in chv_crtc_clock_get()
8114 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); in chv_crtc_clock_get()
8115 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); in chv_crtc_clock_get()
8116 mutex_unlock(&dev_priv->sb_lock); in chv_crtc_clock_get()
8133 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_get_pipe_config() local
8136 if (!intel_display_power_is_enabled(dev_priv, in i9xx_get_pipe_config()
8229 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_init_pch_refclk() local
8256 has_ck505 = dev_priv->vbt.display_clock_mode; in ironlake_init_pch_refclk()
8291 if (intel_panel_use_ssc(dev_priv) && can_ssc) in ironlake_init_pch_refclk()
8295 if (intel_panel_use_ssc(dev_priv) && can_ssc) in ironlake_init_pch_refclk()
8322 if (intel_panel_use_ssc(dev_priv) && can_ssc) { in ironlake_init_pch_refclk()
8337 if (intel_panel_use_ssc(dev_priv) && can_ssc) { in ironlake_init_pch_refclk()
8375 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) in lpt_reset_fdi_mphy() argument
8397 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) in lpt_program_fdi_mphy() argument
8401 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); in lpt_program_fdi_mphy()
8404 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
8406 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); in lpt_program_fdi_mphy()
8408 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
8410 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); in lpt_program_fdi_mphy()
8412 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
8414 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); in lpt_program_fdi_mphy()
8416 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
8418 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); in lpt_program_fdi_mphy()
8420 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
8422 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); in lpt_program_fdi_mphy()
8425 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
8427 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); in lpt_program_fdi_mphy()
8430 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
8432 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); in lpt_program_fdi_mphy()
8435 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
8437 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); in lpt_program_fdi_mphy()
8440 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
8442 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); in lpt_program_fdi_mphy()
8445 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
8447 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); in lpt_program_fdi_mphy()
8450 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
8452 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); in lpt_program_fdi_mphy()
8454 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
8456 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); in lpt_program_fdi_mphy()
8458 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
8460 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); in lpt_program_fdi_mphy()
8463 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
8465 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); in lpt_program_fdi_mphy()
8468 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
8480 struct drm_i915_private *dev_priv = dev->dev_private; in lpt_enable_clkout_dp() local
8488 mutex_lock(&dev_priv->sb_lock); in lpt_enable_clkout_dp()
8490 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); in lpt_enable_clkout_dp()
8493 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); in lpt_enable_clkout_dp()
8498 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); in lpt_enable_clkout_dp()
8500 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); in lpt_enable_clkout_dp()
8503 lpt_reset_fdi_mphy(dev_priv); in lpt_enable_clkout_dp()
8504 lpt_program_fdi_mphy(dev_priv); in lpt_enable_clkout_dp()
8509 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); in lpt_enable_clkout_dp()
8511 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); in lpt_enable_clkout_dp()
8513 mutex_unlock(&dev_priv->sb_lock); in lpt_enable_clkout_dp()
8519 struct drm_i915_private *dev_priv = dev->dev_private; in lpt_disable_clkout_dp() local
8522 mutex_lock(&dev_priv->sb_lock); in lpt_disable_clkout_dp()
8525 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); in lpt_disable_clkout_dp()
8527 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); in lpt_disable_clkout_dp()
8529 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); in lpt_disable_clkout_dp()
8533 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); in lpt_disable_clkout_dp()
8537 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); in lpt_disable_clkout_dp()
8540 mutex_unlock(&dev_priv->sb_lock); in lpt_disable_clkout_dp()
8578 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_get_refclk() local
8602 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { in ironlake_get_refclk()
8604 dev_priv->vbt.lvds_ssc_freq); in ironlake_get_refclk()
8605 return dev_priv->vbt.lvds_ssc_freq; in ironlake_get_refclk()
8613 struct drm_i915_private *dev_priv = crtc->dev->dev_private; in ironlake_set_pipeconf() local
8663 struct drm_i915_private *dev_priv = dev->dev_private; in intel_set_pipe_csc() local
8720 struct drm_i915_private *dev_priv = dev->dev_private; in haswell_set_pipeconf() local
8777 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_compute_clocks() local
8790 ret = dev_priv->display.find_dpll(limit, crtc_state, in ironlake_compute_clocks()
8822 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_compute_dpll() local
8855 if ((intel_panel_use_ssc(dev_priv) && in ironlake_compute_dpll()
8856 dev_priv->vbt.lvds_ssc_freq == 100000) || in ironlake_compute_dpll()
8903 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) in ironlake_compute_dpll()
8981 struct drm_i915_private *dev_priv = dev->dev_private; in intel_pch_transcoder_get_m_n() local
8999 struct drm_i915_private *dev_priv = dev->dev_private; in intel_cpu_transcoder_get_m_n() local
9057 struct drm_i915_private *dev_priv = dev->dev_private; in skylake_get_pfit_config() local
9088 struct drm_i915_private *dev_priv = dev->dev_private; in skylake_get_initial_plane_config() local
9171 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_get_pfit_config() local
9196 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_get_initial_plane_config() local
9264 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_get_pipe_config() local
9267 if (!intel_display_power_is_enabled(dev_priv, in ironlake_get_pipe_config()
9309 if (HAS_PCH_IBX(dev_priv->dev)) { in ironlake_get_pipe_config()
9320 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; in ironlake_get_pipe_config()
9322 WARN_ON(!pll->get_hw_state(dev_priv, pll, in ironlake_get_pipe_config()
9342 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) in assert_can_disable_lcpll() argument
9344 struct drm_device *dev = dev_priv->dev; in assert_can_disable_lcpll()
9373 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); in assert_can_disable_lcpll()
9376 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) in hsw_read_dcomp() argument
9378 struct drm_device *dev = dev_priv->dev; in hsw_read_dcomp()
9386 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) in hsw_write_dcomp() argument
9388 struct drm_device *dev = dev_priv->dev; in hsw_write_dcomp()
9391 mutex_lock(&dev_priv->rps.hw_lock); in hsw_write_dcomp()
9392 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, in hsw_write_dcomp()
9395 mutex_unlock(&dev_priv->rps.hw_lock); in hsw_write_dcomp()
9410 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, in hsw_disable_lcpll() argument
9415 assert_can_disable_lcpll(dev_priv); in hsw_disable_lcpll()
9437 val = hsw_read_dcomp(dev_priv); in hsw_disable_lcpll()
9439 hsw_write_dcomp(dev_priv, val); in hsw_disable_lcpll()
9442 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, in hsw_disable_lcpll()
9458 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) in hsw_restore_lcpll() argument
9472 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); in hsw_restore_lcpll()
9480 val = hsw_read_dcomp(dev_priv); in hsw_restore_lcpll()
9483 hsw_write_dcomp(dev_priv, val); in hsw_restore_lcpll()
9502 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); in hsw_restore_lcpll()
9503 intel_update_cdclk(dev_priv->dev); in hsw_restore_lcpll()
9529 void hsw_enable_pc8(struct drm_i915_private *dev_priv) in hsw_enable_pc8() argument
9531 struct drm_device *dev = dev_priv->dev; in hsw_enable_pc8()
9543 hsw_disable_lcpll(dev_priv, true, true); in hsw_enable_pc8()
9546 void hsw_disable_pc8(struct drm_i915_private *dev_priv) in hsw_disable_pc8() argument
9548 struct drm_device *dev = dev_priv->dev; in hsw_disable_pc8()
9553 hsw_restore_lcpll(dev_priv); in hsw_disable_pc8()
9604 struct drm_i915_private *dev_priv = dev->dev_private; in broadwell_set_cdclk() local
9616 mutex_lock(&dev_priv->rps.hw_lock); in broadwell_set_cdclk()
9617 ret = sandybridge_pcode_write(dev_priv, in broadwell_set_cdclk()
9619 mutex_unlock(&dev_priv->rps.hw_lock); in broadwell_set_cdclk()
9668 mutex_lock(&dev_priv->rps.hw_lock); in broadwell_set_cdclk()
9669 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); in broadwell_set_cdclk()
9670 mutex_unlock(&dev_priv->rps.hw_lock); in broadwell_set_cdclk()
9674 WARN(cdclk != dev_priv->cdclk_freq, in broadwell_set_cdclk()
9676 cdclk, dev_priv->cdclk_freq); in broadwell_set_cdclk()
9681 struct drm_i915_private *dev_priv = to_i915(state->dev); in broadwell_modeset_calc_cdclk() local
9702 if (cdclk > dev_priv->max_cdclk_freq) { in broadwell_modeset_calc_cdclk()
9704 cdclk, dev_priv->max_cdclk_freq); in broadwell_modeset_calc_cdclk()
9705 cdclk = dev_priv->max_cdclk_freq; in broadwell_modeset_calc_cdclk()
9732 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, in bxt_get_ddi_pll() argument
9754 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, in skylake_get_ddi_pll() argument
9785 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, in haswell_get_ddi_pll() argument
9807 struct drm_i915_private *dev_priv = dev->dev_private; in haswell_get_ddi_port_state() local
9817 skylake_get_ddi_pll(dev_priv, port, pipe_config); in haswell_get_ddi_port_state()
9819 bxt_get_ddi_pll(dev_priv, port, pipe_config); in haswell_get_ddi_port_state()
9821 haswell_get_ddi_pll(dev_priv, port, pipe_config); in haswell_get_ddi_port_state()
9824 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; in haswell_get_ddi_port_state()
9826 WARN_ON(!pll->get_hw_state(dev_priv, pll, in haswell_get_ddi_port_state()
9851 struct drm_i915_private *dev_priv = dev->dev_private; in haswell_get_pipe_config() local
9855 if (!intel_display_power_is_enabled(dev_priv, in haswell_get_pipe_config()
9884 if (!intel_display_power_is_enabled(dev_priv, in haswell_get_pipe_config()
9907 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { in haswell_get_pipe_config()
9931 struct drm_i915_private *dev_priv = dev->dev_private; in i845_update_cursor() local
9993 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_update_cursor() local
10041 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crtc_update_cursor() local
10232 struct drm_i915_private *dev_priv = dev->dev_private; in mode_fits_in_fbdev() local
10236 if (!dev_priv->fbdev) in mode_fits_in_fbdev()
10239 if (!dev_priv->fbdev->fb) in mode_fits_in_fbdev()
10242 obj = dev_priv->fbdev->fb->obj; in mode_fits_in_fbdev()
10245 fb = &dev_priv->fbdev->fb->base; in mode_fits_in_fbdev()
10529 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_pll_refclk() local
10533 return dev_priv->vbt.lvds_ssc_freq; in i9xx_pll_refclk()
10547 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_crtc_clock_get() local
10674 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crtc_mode_get() local
10720 struct drm_i915_private *dev_priv = dev->dev_private; in intel_mark_busy() local
10722 if (dev_priv->mm.busy) in intel_mark_busy()
10725 intel_runtime_pm_get(dev_priv); in intel_mark_busy()
10726 i915_update_gfx_val(dev_priv); in intel_mark_busy()
10728 gen6_rps_busy(dev_priv); in intel_mark_busy()
10729 dev_priv->mm.busy = true; in intel_mark_busy()
10734 struct drm_i915_private *dev_priv = dev->dev_private; in intel_mark_idle() local
10736 if (!dev_priv->mm.busy) in intel_mark_idle()
10739 dev_priv->mm.busy = false; in intel_mark_idle()
10744 intel_runtime_pm_put(dev_priv); in intel_mark_idle()
10826 struct drm_i915_private *dev_priv = dev->dev_private; in intel_finish_page_flip() local
10827 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in intel_finish_page_flip()
10834 struct drm_i915_private *dev_priv = dev->dev_private; in intel_finish_page_flip_plane() local
10835 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; in intel_finish_page_flip_plane()
10849 struct drm_i915_private *dev_priv = dev->dev_private; in page_flip_finished() local
10851 if (i915_reset_in_progress(&dev_priv->gpu_error) || in page_flip_finished()
10852 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) in page_flip_finished()
10888 struct drm_i915_private *dev_priv = dev->dev_private; in intel_prepare_page_flip() local
10890 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); in intel_prepare_page_flip()
10992 struct drm_i915_private *dev_priv = dev->dev_private; in intel_gen4_queue_flip() local
11031 struct drm_i915_private *dev_priv = dev->dev_private; in intel_gen6_queue_flip() local
11185 struct drm_i915_private *dev_priv = dev->dev_private; in skl_do_mmio_flip() local
11231 struct drm_i915_private *dev_priv = dev->dev_private; in ilk_do_mmio_flip() local
11333 struct drm_i915_private *dev_priv = dev->dev_private; in __intel_pageflip_stall_check() local
11374 struct drm_i915_private *dev_priv = dev->dev_private; in intel_check_page_flip() local
11375 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in intel_check_page_flip()
11404 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crtc_page_flip() local
11437 if (i915_terminally_wedged(&dev_priv->gpu_error)) in intel_crtc_page_flip()
11475 flush_workqueue(dev_priv->wq); in intel_crtc_page_flip()
11491 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); in intel_crtc_page_flip()
11497 ring = &dev_priv->ring[BCS]; in intel_crtc_page_flip()
11502 ring = &dev_priv->ring[BCS]; in intel_crtc_page_flip()
11506 ring = &dev_priv->ring[BCS]; in intel_crtc_page_flip()
11508 ring = &dev_priv->ring[RCS]; in intel_crtc_page_flip()
11543 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, in intel_crtc_page_flip()
11663 struct drm_i915_private *dev_priv = dev->dev_private; in intel_plane_atomic_calc_changes() local
11772 dev_priv->fbc.crtc == intel_crtc && in intel_plane_atomic_calc_changes()
11852 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crtc_atomic_check() local
11869 dev_priv->display.crtc_compute_clock && in intel_crtc_atomic_check()
11871 ret = dev_priv->display.crtc_compute_clock(intel_crtc, in intel_crtc_atomic_check()
12638 struct drm_i915_private *dev_priv = dev->dev_private; in check_wm_state() local
12646 skl_ddb_get_hw_state(dev_priv, &hw_ddb); in check_wm_state()
12647 sw_ddb = &dev_priv->wm.skl_hw.ddb; in check_wm_state()
12657 for_each_plane(dev_priv, pipe, plane) { in check_wm_state()
12750 struct drm_i915_private *dev_priv = dev->dev_private; in check_crtc_state() local
12774 active = dev_priv->display.get_pipe_config(intel_crtc, in check_crtc_state()
12778 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in check_crtc_state()
12779 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in check_crtc_state()
12824 struct drm_i915_private *dev_priv = dev->dev_private; in check_shared_dpll_state() local
12829 for (i = 0; i < dev_priv->num_shared_dpll; i++) { in check_shared_dpll_state()
12830 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; in check_shared_dpll_state()
12838 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); in check_shared_dpll_state()
12934 struct drm_i915_private *dev_priv = to_i915(dev); in intel_modeset_clear_plls() local
12942 if (!dev_priv->display.crtc_compute_clock) in intel_modeset_clear_plls()
13061 struct drm_i915_private *dev_priv = dev->dev_private; in intel_modeset_checks() local
13076 if (dev_priv->display.modeset_calc_cdclk) { in intel_modeset_checks()
13079 ret = dev_priv->display.modeset_calc_cdclk(state); in intel_modeset_checks()
13082 if (!ret && cdclk != dev_priv->cdclk_freq) in intel_modeset_checks()
13088 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq; in intel_modeset_checks()
13199 struct drm_i915_private *dev_priv = dev->dev_private; in intel_atomic_commit() local
13228 dev_priv->display.crtc_disable(crtc); in intel_atomic_commit()
13255 dev_priv->display.crtc_enable(crtc); in intel_atomic_commit()
13271 modeset_put_power_domains(dev_priv, put_domains); in intel_atomic_commit()
13338 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, in ibx_pch_dpll_get_hw_state() argument
13344 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) in ibx_pch_dpll_get_hw_state()
13355 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, in ibx_pch_dpll_mode_set() argument
13362 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, in ibx_pch_dpll_enable() argument
13366 ibx_assert_pch_refclk_enabled(dev_priv); in ibx_pch_dpll_enable()
13384 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, in ibx_pch_dpll_disable() argument
13387 struct drm_device *dev = dev_priv->dev; in ibx_pch_dpll_disable()
13393 assert_pch_transcoder_disabled(dev_priv, crtc->pipe); in ibx_pch_dpll_disable()
13408 struct drm_i915_private *dev_priv = dev->dev_private; in ibx_pch_dpll_init() local
13411 dev_priv->num_shared_dpll = 2; in ibx_pch_dpll_init()
13413 for (i = 0; i < dev_priv->num_shared_dpll; i++) { in ibx_pch_dpll_init()
13414 dev_priv->shared_dplls[i].id = i; in ibx_pch_dpll_init()
13415 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; in ibx_pch_dpll_init()
13416 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; in ibx_pch_dpll_init()
13417 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; in ibx_pch_dpll_init()
13418 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; in ibx_pch_dpll_init()
13419 dev_priv->shared_dplls[i].get_hw_state = in ibx_pch_dpll_init()
13426 struct drm_i915_private *dev_priv = dev->dev_private; in intel_shared_dpll_init() local
13433 dev_priv->num_shared_dpll = 0; in intel_shared_dpll_init()
13435 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); in intel_shared_dpll_init()
13514 struct drm_i915_private *dev_priv; in skl_max_scale() local
13521 dev_priv = dev->dev_private; in skl_max_scale()
13573 struct drm_i915_private *dev_priv = dev->dev_private; in intel_commit_primary_plane() local
13587 dev_priv->display.update_primary_plane(crtc, fb, in intel_commit_primary_plane()
13597 struct drm_i915_private *dev_priv = dev->dev_private; in intel_disable_primary_plane() local
13599 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); in intel_disable_primary_plane()
13902 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crtc_init() local
13967 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || in intel_crtc_init()
13968 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); in intel_crtc_init()
13969 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; in intel_crtc_init()
13970 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; in intel_crtc_init()
14038 struct drm_i915_private *dev_priv = dev->dev_private; in has_edp_a() local
14054 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crt_present() local
14065 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) in intel_crt_present()
14073 struct drm_i915_private *dev_priv = dev->dev_private; in intel_setup_outputs() local
14118 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || in intel_setup_outputs()
14119 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || in intel_setup_outputs()
14120 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) in intel_setup_outputs()
14499 struct drm_i915_private *dev_priv = dev->dev_private; in intel_init_display() local
14502 dev_priv->display.find_dpll = g4x_find_best_dpll; in intel_init_display()
14504 dev_priv->display.find_dpll = chv_find_best_dpll; in intel_init_display()
14506 dev_priv->display.find_dpll = vlv_find_best_dpll; in intel_init_display()
14508 dev_priv->display.find_dpll = pnv_find_best_dpll; in intel_init_display()
14510 dev_priv->display.find_dpll = i9xx_find_best_dpll; in intel_init_display()
14513 dev_priv->display.get_pipe_config = haswell_get_pipe_config; in intel_init_display()
14514 dev_priv->display.get_initial_plane_config = in intel_init_display()
14516 dev_priv->display.crtc_compute_clock = in intel_init_display()
14518 dev_priv->display.crtc_enable = haswell_crtc_enable; in intel_init_display()
14519 dev_priv->display.crtc_disable = haswell_crtc_disable; in intel_init_display()
14520 dev_priv->display.update_primary_plane = in intel_init_display()
14523 dev_priv->display.get_pipe_config = haswell_get_pipe_config; in intel_init_display()
14524 dev_priv->display.get_initial_plane_config = in intel_init_display()
14526 dev_priv->display.crtc_compute_clock = in intel_init_display()
14528 dev_priv->display.crtc_enable = haswell_crtc_enable; in intel_init_display()
14529 dev_priv->display.crtc_disable = haswell_crtc_disable; in intel_init_display()
14530 dev_priv->display.update_primary_plane = in intel_init_display()
14533 dev_priv->display.get_pipe_config = ironlake_get_pipe_config; in intel_init_display()
14534 dev_priv->display.get_initial_plane_config = in intel_init_display()
14536 dev_priv->display.crtc_compute_clock = in intel_init_display()
14538 dev_priv->display.crtc_enable = ironlake_crtc_enable; in intel_init_display()
14539 dev_priv->display.crtc_disable = ironlake_crtc_disable; in intel_init_display()
14540 dev_priv->display.update_primary_plane = in intel_init_display()
14543 dev_priv->display.get_pipe_config = i9xx_get_pipe_config; in intel_init_display()
14544 dev_priv->display.get_initial_plane_config = in intel_init_display()
14546 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; in intel_init_display()
14547 dev_priv->display.crtc_enable = valleyview_crtc_enable; in intel_init_display()
14548 dev_priv->display.crtc_disable = i9xx_crtc_disable; in intel_init_display()
14549 dev_priv->display.update_primary_plane = in intel_init_display()
14552 dev_priv->display.get_pipe_config = i9xx_get_pipe_config; in intel_init_display()
14553 dev_priv->display.get_initial_plane_config = in intel_init_display()
14555 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; in intel_init_display()
14556 dev_priv->display.crtc_enable = i9xx_crtc_enable; in intel_init_display()
14557 dev_priv->display.crtc_disable = i9xx_crtc_disable; in intel_init_display()
14558 dev_priv->display.update_primary_plane = in intel_init_display()
14564 dev_priv->display.get_display_clock_speed = in intel_init_display()
14567 dev_priv->display.get_display_clock_speed = in intel_init_display()
14570 dev_priv->display.get_display_clock_speed = in intel_init_display()
14573 dev_priv->display.get_display_clock_speed = in intel_init_display()
14576 dev_priv->display.get_display_clock_speed = in intel_init_display()
14579 dev_priv->display.get_display_clock_speed = in intel_init_display()
14583 dev_priv->display.get_display_clock_speed = in intel_init_display()
14586 dev_priv->display.get_display_clock_speed = in intel_init_display()
14589 dev_priv->display.get_display_clock_speed = in intel_init_display()
14592 dev_priv->display.get_display_clock_speed = in intel_init_display()
14595 dev_priv->display.get_display_clock_speed = in intel_init_display()
14598 dev_priv->display.get_display_clock_speed = in intel_init_display()
14601 dev_priv->display.get_display_clock_speed = in intel_init_display()
14604 dev_priv->display.get_display_clock_speed = in intel_init_display()
14607 dev_priv->display.get_display_clock_speed = in intel_init_display()
14610 dev_priv->display.get_display_clock_speed = in intel_init_display()
14613 dev_priv->display.get_display_clock_speed = in intel_init_display()
14617 dev_priv->display.get_display_clock_speed = in intel_init_display()
14622 dev_priv->display.fdi_link_train = ironlake_fdi_link_train; in intel_init_display()
14624 dev_priv->display.fdi_link_train = gen6_fdi_link_train; in intel_init_display()
14627 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; in intel_init_display()
14629 dev_priv->display.fdi_link_train = hsw_fdi_link_train; in intel_init_display()
14631 dev_priv->display.modeset_commit_cdclk = in intel_init_display()
14633 dev_priv->display.modeset_calc_cdclk = in intel_init_display()
14637 dev_priv->display.modeset_commit_cdclk = in intel_init_display()
14639 dev_priv->display.modeset_calc_cdclk = in intel_init_display()
14642 dev_priv->display.modeset_commit_cdclk = in intel_init_display()
14644 dev_priv->display.modeset_calc_cdclk = in intel_init_display()
14650 dev_priv->display.queue_flip = intel_gen2_queue_flip; in intel_init_display()
14654 dev_priv->display.queue_flip = intel_gen3_queue_flip; in intel_init_display()
14659 dev_priv->display.queue_flip = intel_gen4_queue_flip; in intel_init_display()
14663 dev_priv->display.queue_flip = intel_gen6_queue_flip; in intel_init_display()
14667 dev_priv->display.queue_flip = intel_gen7_queue_flip; in intel_init_display()
14673 dev_priv->display.queue_flip = intel_default_queue_flip; in intel_init_display()
14676 mutex_init(&dev_priv->pps_mutex); in intel_init_display()
14686 struct drm_i915_private *dev_priv = dev->dev_private; in quirk_pipea_force() local
14688 dev_priv->quirks |= QUIRK_PIPEA_FORCE; in quirk_pipea_force()
14694 struct drm_i915_private *dev_priv = dev->dev_private; in quirk_pipeb_force() local
14696 dev_priv->quirks |= QUIRK_PIPEB_FORCE; in quirk_pipeb_force()
14705 struct drm_i915_private *dev_priv = dev->dev_private; in quirk_ssc_force_disable() local
14706 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; in quirk_ssc_force_disable()
14716 struct drm_i915_private *dev_priv = dev->dev_private; in quirk_invert_brightness() local
14717 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; in quirk_invert_brightness()
14724 struct drm_i915_private *dev_priv = dev->dev_private; in quirk_backlight_present() local
14725 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; in quirk_backlight_present()
14850 struct drm_i915_private *dev_priv = dev->dev_private; in i915_disable_vga() local
14876 struct drm_i915_private *dev_priv = dev->dev_private; in intel_modeset_init() local
14910 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { in intel_modeset_init()
14913 dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); in intel_modeset_init()
14914 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; in intel_modeset_init()
14943 dev->mode_config.fb_base = dev_priv->gtt.mappable_base; in intel_modeset_init()
14949 for_each_pipe(dev_priv, pipe) { in intel_modeset_init()
14951 for_each_sprite(dev_priv, pipe, sprite) { in intel_modeset_init()
14959 intel_update_czclk(dev_priv); in intel_modeset_init()
14969 intel_fbc_disable(dev_priv); in intel_modeset_init()
14988 dev_priv->display.get_initial_plane_config(crtc, in intel_modeset_init()
15027 struct drm_i915_private *dev_priv = dev->dev_private; in intel_check_plane_mapping() local
15056 struct drm_i915_private *dev_priv = dev->dev_private; in intel_sanitize_crtc() local
15098 if (dev_priv->quirks & QUIRK_PIPEA_FORCE && in intel_sanitize_crtc()
15213 struct drm_i915_private *dev_priv = dev->dev_private; in i915_redisable_vga_power_on() local
15224 struct drm_i915_private *dev_priv = dev->dev_private; in i915_redisable_vga() local
15233 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) in i915_redisable_vga()
15241 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in primary_get_hw_state() local
15262 struct drm_i915_private *dev_priv = dev->dev_private; in intel_modeset_readout_hw_state() local
15274 crtc->active = dev_priv->display.get_pipe_config(crtc, in intel_modeset_readout_hw_state()
15287 for (i = 0; i < dev_priv->num_shared_dpll; i++) { in intel_modeset_readout_hw_state()
15288 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; in intel_modeset_readout_hw_state()
15290 pll->on = pll->get_hw_state(dev_priv, pll, in intel_modeset_readout_hw_state()
15305 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); in intel_modeset_readout_hw_state()
15312 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); in intel_modeset_readout_hw_state()
15380 struct drm_i915_private *dev_priv = dev->dev_private; in intel_modeset_setup_hw_state() local
15393 for_each_pipe(dev_priv, pipe) { in intel_modeset_setup_hw_state()
15394 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); in intel_modeset_setup_hw_state()
15402 for (i = 0; i < dev_priv->num_shared_dpll; i++) { in intel_modeset_setup_hw_state()
15403 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; in intel_modeset_setup_hw_state()
15410 pll->disable(dev_priv, pll); in intel_modeset_setup_hw_state()
15426 modeset_put_power_domains(dev_priv, put_domains); in intel_modeset_setup_hw_state()
15428 intel_display_set_init_power(dev_priv, false); in intel_modeset_setup_hw_state()
15537 struct drm_i915_private *dev_priv = dev->dev_private; in intel_modeset_cleanup() local
15549 intel_irq_uninstall(dev_priv); in intel_modeset_cleanup()
15559 intel_fbc_disable(dev_priv); in intel_modeset_cleanup()
15604 struct drm_i915_private *dev_priv = dev->dev_private; in intel_modeset_vga_set_state() local
15608 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { in intel_modeset_vga_set_state()
15621 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { in intel_modeset_vga_set_state()
15676 struct drm_i915_private *dev_priv = dev->dev_private; in intel_display_capture_error_state() local
15696 for_each_pipe(dev_priv, i) { in intel_display_capture_error_state()
15698 __intel_display_power_is_enabled(dev_priv, in intel_display_capture_error_state()
15727 if (HAS_DDI(dev_priv->dev)) in intel_display_capture_error_state()
15734 __intel_display_power_is_enabled(dev_priv, in intel_display_capture_error_state()
15760 struct drm_i915_private *dev_priv = dev->dev_private; in intel_display_print_error_state() local
15770 for_each_pipe(dev_priv, i) { in intel_display_print_error_state()