Lines Matching refs:adjusted_mode
1084 intel_crtc->config->base.adjusted_mode.crtc_clock; in intel_crtc_active()
3986 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; in lpt_program_iclkip()
4444 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; in skl_update_scaler_crtc() local
4452 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); in skl_update_scaler_crtc()
6036 crtc_state->base.adjusted_mode.crtc_clock); in intel_mode_max_pixclk()
6571 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in ironlake_fdi_compute_config() local
6585 fdi_dotclock = adjusted_mode->crtc_clock; in ironlake_fdi_compute_config()
6650 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_crtc_compute_config() local
6664 adjusted_mode->crtc_clock > clock_limit * 9 / 10) { in intel_crtc_compute_config()
6669 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) in intel_crtc_compute_config()
6687 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) in intel_crtc_compute_config()
7702 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; in intel_set_pipe_timings() local
7708 crtc_vtotal = adjusted_mode->crtc_vtotal; in intel_set_pipe_timings()
7709 crtc_vblank_end = adjusted_mode->crtc_vblank_end; in intel_set_pipe_timings()
7711 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { in intel_set_pipe_timings()
7717 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; in intel_set_pipe_timings()
7719 vsyncshift = adjusted_mode->crtc_hsync_start - in intel_set_pipe_timings()
7720 adjusted_mode->crtc_htotal / 2; in intel_set_pipe_timings()
7722 vsyncshift += adjusted_mode->crtc_htotal; in intel_set_pipe_timings()
7729 (adjusted_mode->crtc_hdisplay - 1) | in intel_set_pipe_timings()
7730 ((adjusted_mode->crtc_htotal - 1) << 16)); in intel_set_pipe_timings()
7732 (adjusted_mode->crtc_hblank_start - 1) | in intel_set_pipe_timings()
7733 ((adjusted_mode->crtc_hblank_end - 1) << 16)); in intel_set_pipe_timings()
7735 (adjusted_mode->crtc_hsync_start - 1) | in intel_set_pipe_timings()
7736 ((adjusted_mode->crtc_hsync_end - 1) << 16)); in intel_set_pipe_timings()
7739 (adjusted_mode->crtc_vdisplay - 1) | in intel_set_pipe_timings()
7742 (adjusted_mode->crtc_vblank_start - 1) | in intel_set_pipe_timings()
7745 (adjusted_mode->crtc_vsync_start - 1) | in intel_set_pipe_timings()
7746 ((adjusted_mode->crtc_vsync_end - 1) << 16)); in intel_set_pipe_timings()
7773 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7774 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7776 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7777 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7779 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7780 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7783 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7784 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7786 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7787 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7789 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7790 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7793 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; in intel_get_pipe_timings()
7794 pipe_config->base.adjusted_mode.crtc_vtotal += 1; in intel_get_pipe_timings()
7795 pipe_config->base.adjusted_mode.crtc_vblank_end += 1; in intel_get_pipe_timings()
7809 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; in intel_mode_from_pipe_config()
7810 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; in intel_mode_from_pipe_config()
7811 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; in intel_mode_from_pipe_config()
7812 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; in intel_mode_from_pipe_config()
7814 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; in intel_mode_from_pipe_config()
7815 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; in intel_mode_from_pipe_config()
7816 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; in intel_mode_from_pipe_config()
7817 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; in intel_mode_from_pipe_config()
7819 mode->flags = pipe_config->base.adjusted_mode.flags; in intel_mode_from_pipe_config()
7822 mode->clock = pipe_config->base.adjusted_mode.crtc_clock; in intel_mode_from_pipe_config()
7823 mode->flags |= pipe_config->base.adjusted_mode.flags; in intel_mode_from_pipe_config()
7877 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { in i9xx_set_pipeconf()
8221 pipe_config->base.adjusted_mode.crtc_clock = in i9xx_get_pipe_config()
8641 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) in ironlake_set_pipeconf()
8731 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) in haswell_set_pipeconf()
10665 pipe_config->base.adjusted_mode.crtc_clock = in ironlake_pch_clock_get()
12041 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); in intel_dump_pipe_config()
12042 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); in intel_dump_pipe_config()
12236 if (!(pipe_config->base.adjusted_mode.flags & in intel_modeset_pipe_config()
12238 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; in intel_modeset_pipe_config()
12240 if (!(pipe_config->base.adjusted_mode.flags & in intel_modeset_pipe_config()
12242 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; in intel_modeset_pipe_config()
12267 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, in intel_modeset_pipe_config()
12289 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock in intel_modeset_pipe_config()
12332 crtc->hwmode = crtc->state->adjusted_mode; in intel_modeset_update_crtc_state()
12544 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); in intel_pipe_config_compare()
12545 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); in intel_pipe_config_compare()
12546 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); in intel_pipe_config_compare()
12547 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); in intel_pipe_config_compare()
12548 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); in intel_pipe_config_compare()
12549 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); in intel_pipe_config_compare()
12551 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); in intel_pipe_config_compare()
12552 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); in intel_pipe_config_compare()
12553 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); in intel_pipe_config_compare()
12554 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); in intel_pipe_config_compare()
12555 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); in intel_pipe_config_compare()
12556 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); in intel_pipe_config_compare()
12567 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, in intel_pipe_config_compare()
12571 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, in intel_pipe_config_compare()
12573 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, in intel_pipe_config_compare()
12575 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, in intel_pipe_config_compare()
12577 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, in intel_pipe_config_compare()
12622 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); in intel_pipe_config_compare()
12888 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), in ironlake_check_encoder_dotclock()
12890 pipe_config->base.adjusted_mode.crtc_clock, dotclock); in ironlake_check_encoder_dotclock()
12916 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; in update_scanline_offset() local
12919 vtotal = adjusted_mode->crtc_vtotal; in update_scanline_offset()
12920 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) in update_scanline_offset()
13522 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; in skl_max_scale()
15341 crtc->base.hwmode = crtc->config->base.adjusted_mode; in intel_modeset_readout_hw_state()
15346 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); in intel_modeset_readout_hw_state()