1616 	POSTING_READ(reg);  in vlv_enable_pll()
1623 	POSTING_READ(DPLL_MD(crtc->pipe));  in vlv_enable_pll()
1627 	POSTING_READ(reg);  in vlv_enable_pll()
1630 	POSTING_READ(reg);  in vlv_enable_pll()
1633 	POSTING_READ(reg);  in vlv_enable_pll()
1673 	POSTING_READ(DPLL_MD(pipe));  in chv_enable_pll()
1727 	POSTING_READ(reg);  in i9xx_enable_pll()
1744 	POSTING_READ(reg);  in i9xx_enable_pll()
1747 	POSTING_READ(reg);  in i9xx_enable_pll()
1750 	POSTING_READ(reg);  in i9xx_enable_pll()
1788 	POSTING_READ(DPLL(pipe));  in i9xx_disable_pll()
1806 	POSTING_READ(DPLL(pipe));  in vlv_disable_pll()
1824 	POSTING_READ(DPLL(pipe));  in chv_disable_pll()
2156 	POSTING_READ(reg);  in intel_enable_pipe()
2707 		POSTING_READ(reg);  in i9xx_update_primary_plane()
2812 	POSTING_READ(reg);  in i9xx_update_primary_plane()
2834 		POSTING_READ(reg);  in ironlake_update_primary_plane()
2916 	POSTING_READ(reg);  in ironlake_update_primary_plane()
3114 		POSTING_READ(PLANE_CTL(pipe, 0));  in skylake_update_primary_plane()
3189 	POSTING_READ(PLANE_SURF(pipe, 0));  in skylake_update_primary_plane()
3430 	POSTING_READ(reg);  in intel_fdi_normal_train()
3476 	POSTING_READ(reg);  in ironlake_fdi_link_train()
3511 	POSTING_READ(reg);  in ironlake_fdi_link_train()
3556 	POSTING_READ(reg);  in gen6_fdi_link_train()
3585 	POSTING_READ(reg);  in gen6_fdi_link_train()
3595 		POSTING_READ(reg);  in gen6_fdi_link_train()
3638 	POSTING_READ(reg);  in gen6_fdi_link_train()
3648 		POSTING_READ(reg);  in gen6_fdi_link_train()
3688 	POSTING_READ(reg);  in ivb_manual_fdi_link_train()
3730 		POSTING_READ(reg);  in ivb_manual_fdi_link_train()
3765 		POSTING_READ(reg);  in ivb_manual_fdi_link_train()
3806 	POSTING_READ(reg);  in ironlake_fdi_pll_enable()
3813 	POSTING_READ(reg);  in ironlake_fdi_pll_enable()
3822 		POSTING_READ(reg);  in ironlake_fdi_pll_enable()
3844 	POSTING_READ(reg);  in ironlake_fdi_pll_disable()
3852 	POSTING_READ(reg);  in ironlake_fdi_pll_disable()
3868 	POSTING_READ(reg);  in ironlake_fdi_disable()
3876 	POSTING_READ(reg);  in ironlake_fdi_disable()
3904 	POSTING_READ(reg);  in ironlake_fdi_disable()
4112 	POSTING_READ(SOUTH_CHICKEN1);  in cpt_set_fdi_bc_bifurcation()
4631 		POSTING_READ(IPS_CTL);  in hsw_disable_ips()
5621 	POSTING_READ(DBUF_CTL);  in broxton_init_cdclk()
5634 	POSTING_READ(DBUF_CTL);  in broxton_uninit_cdclk()
5698 	POSTING_READ(CDCLK_CTL);  in skl_dpll0_enable()
5722 	POSTING_READ(DPLL_CTRL1);  in skl_dpll0_enable()
5794 	POSTING_READ(CDCLK_CTL);  in skl_set_cdclk()
5808 	POSTING_READ(DBUF_CTL);  in skl_uninit_cdclk()
5853 	POSTING_READ(DBUF_CTL);  in skl_init_cdclk()
7890 	POSTING_READ(PIPECONF(intel_crtc->pipe));  in i9xx_set_pipeconf()
8330 		POSTING_READ(PCH_DREF_CONTROL);  in ironlake_init_pch_refclk()
8346 		POSTING_READ(PCH_DREF_CONTROL);  in ironlake_init_pch_refclk()
8357 		POSTING_READ(PCH_DREF_CONTROL);  in ironlake_init_pch_refclk()
8368 		POSTING_READ(PCH_DREF_CONTROL);  in ironlake_init_pch_refclk()
8650 	POSTING_READ(PIPECONF(pipe));  in ironlake_set_pipeconf()
8737 	POSTING_READ(PIPECONF(cpu_transcoder));  in haswell_set_pipeconf()
8740 	POSTING_READ(GAMMA_MODE(intel_crtc->pipe));  in haswell_set_pipeconf()
9398 		POSTING_READ(D_COMP_BDW);  in hsw_write_dcomp()
9432 	POSTING_READ(LCPLL_CTL);  in hsw_disable_lcpll()
9450 		POSTING_READ(LCPLL_CTL);  in hsw_disable_lcpll()
9477 		POSTING_READ(LCPLL_CTL);  in hsw_restore_lcpll()
9969 		POSTING_READ(CURCNTR(PIPE_A));  in i845_update_cursor()
9985 		POSTING_READ(CURCNTR(PIPE_A));  in i845_update_cursor()
10025 		POSTING_READ(CURCNTR(pipe));  in i9xx_update_cursor()
10031 	POSTING_READ(CURBASE(pipe));  in i9xx_update_cursor()
11224 	POSTING_READ(PLANE_SURF(pipe, 0));  in skl_do_mmio_flip()
11249 	POSTING_READ(DSPSURF(intel_crtc->plane));  in ilk_do_mmio_flip()
13371 	POSTING_READ(PCH_DPLL(pll->id));  in ibx_pch_dpll_enable()
13380 	POSTING_READ(PCH_DPLL(pll->id));  in ibx_pch_dpll_enable()
13397 	POSTING_READ(PCH_DPLL(pll->id));  in ibx_pch_dpll_disable()
14863 	POSTING_READ(vga_reg);  in i915_disable_vga()