Lines Matching refs:INTEL_OUTPUT_LVDS
559 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { in intel_ironlake_limit()
583 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { in intel_g4x_limit()
612 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) in intel_limit()
621 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) in intel_limit()
626 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) in intel_limit()
747 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { in i9xx_select_p2_div()
6679 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && in intel_crtc_compute_config()
7149 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && in i9xx_get_refclk()
7192 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && in i9xx_update_pll_dividers()
7599 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) in i9xx_compute_dpll()
7642 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && in i9xx_compute_dpll()
7672 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { in i8xx_compute_dpll()
7686 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && in i8xx_compute_dpll()
8241 case INTEL_OUTPUT_LVDS: in ironlake_init_pch_refclk()
8593 case INTEL_OUTPUT_LVDS: in ironlake_get_refclk()
8838 case INTEL_OUTPUT_LVDS: in ironlake_compute_dpll()
8924 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); in ironlake_crtc_compute_clock()