Lines Matching refs:INTEL_INFO
1138 if (INTEL_INFO(dev)->gen >= 4) { in intel_wait_for_pipe_off()
1261 if (INTEL_INFO(dev_priv->dev)->gen == 5) in assert_fdi_tx_pll_enabled()
1393 if (INTEL_INFO(dev)->gen >= 4) { in assert_planes_disabled()
1418 if (INTEL_INFO(dev)->gen >= 9) { in assert_sprites_disabled()
1432 } else if (INTEL_INFO(dev)->gen >= 7) { in assert_sprites_disabled()
1437 } else if (INTEL_INFO(dev)->gen >= 5) { in assert_sprites_disabled()
1698 BUG_ON(INTEL_INFO(dev)->gen >= 5); in i9xx_enable_pll()
1730 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_enable_pll()
1930 if (INTEL_INFO(dev)->gen < 5) in intel_disable_shared_dpll()
2212 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) in need_vtd_wa()
2319 if (INTEL_INFO(dev_priv)->gen >= 9) in intel_linear_alignment()
2324 else if (INTEL_INFO(dev_priv)->gen >= 4) in intel_linear_alignment()
2351 if (INTEL_INFO(dev)->gen >= 9) in intel_pin_and_fence_fb_obj()
2360 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, in intel_pin_and_fence_fb_obj()
2703 if (INTEL_INFO(dev)->gen >= 4) in i9xx_update_primary_plane()
2721 if (INTEL_INFO(dev)->gen < 4) { in i9xx_update_primary_plane()
2766 if (INTEL_INFO(dev)->gen >= 4 && in i9xx_update_primary_plane()
2775 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_update_primary_plane()
2805 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_update_primary_plane()
2933 if (INTEL_INFO(dev)->gen == 2) in intel_fb_stride_alignment()
3247 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) in intel_prepare_reset()
3274 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { in intel_finish_reset()
3385 if (INTEL_INFO(dev)->gen >= 9) { in intel_update_pipe_config()
4292 } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv)) in intel_get_shared_dpll()
5021 if (INTEL_INFO(dev)->gen >= 9) in haswell_crtc_enable()
5156 if (INTEL_INFO(dev)->gen >= 9) in haswell_crtc_disable()
5383 if (INTEL_INFO(dev_priv)->gen >= 9 || in intel_compute_max_dotclk()
5388 else if (INTEL_INFO(dev_priv)->gen < 4) in intel_compute_max_dotclk()
6520 if (INTEL_INFO(dev)->num_pipes == 2) in ironlake_check_fdi_lanes()
6653 if (INTEL_INFO(dev)->gen < 4) { in intel_crtc_compute_config()
6686 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && in intel_crtc_compute_config()
7252 if (INTEL_INFO(dev)->gen >= 5) { in intel_cpu_transcoder_set_m_n()
7261 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && in intel_cpu_transcoder_set_m_n()
7637 if (INTEL_INFO(dev)->gen >= 4) in i9xx_compute_dpll()
7651 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_compute_dpll()
7725 if (INTEL_INFO(dev)->gen > 3) in intel_set_pipe_timings()
7878 if (INTEL_INFO(dev)->gen < 4 || in i9xx_set_pipeconf()
7980 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) in i9xx_get_pfit_config()
7988 if (INTEL_INFO(dev)->gen < 4) { in i9xx_get_pfit_config()
7998 if (INTEL_INFO(dev)->gen < 5) in i9xx_get_pfit_config()
8055 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_get_initial_plane_config()
8067 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_get_initial_plane_config()
8166 if (INTEL_INFO(dev)->gen < 4) in i9xx_get_pipe_config()
8173 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_get_pipe_config()
8696 if (INTEL_INFO(dev)->gen > 6) { in intel_set_pipe_csc()
8742 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { in haswell_set_pipeconf()
9002 if (INTEL_INFO(dev)->gen >= 5) { in intel_cpu_transcoder_get_m_n()
9014 if (m2_n2 && INTEL_INFO(dev)->gen < 8 && in intel_cpu_transcoder_get_m_n()
9216 if (INTEL_INFO(dev)->gen >= 4) { in ironlake_get_initial_plane_config()
9835 if (INTEL_INFO(dev)->gen < 9 && in haswell_get_ddi_port_state()
9896 if (INTEL_INFO(dev)->gen >= 9) { in haswell_get_pipe_config()
9902 if (INTEL_INFO(dev)->gen >= 9) { in haswell_get_pipe_config()
9908 if (INTEL_INFO(dev)->gen >= 9) in haswell_get_pipe_config()
10727 if (INTEL_INFO(dev)->gen >= 6) in intel_mark_busy()
10741 if (INTEL_INFO(dev)->gen >= 6) in intel_mark_idle()
10862 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) in page_flip_finished()
11168 if (INTEL_INFO(ring->dev)->gen < 5) in use_mmio_flip()
11271 if (INTEL_INFO(mmio_flip->i915)->gen >= 9) in intel_do_mmio_flip()
11360 if (INTEL_INFO(dev)->gen >= 4) in __intel_pageflip_stall_check()
11432 if (INTEL_INFO(dev)->gen > 3 && in intel_crtc_page_flip()
11493 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) in intel_crtc_page_flip()
11503 } else if (INTEL_INFO(dev)->gen >= 7) { in intel_crtc_page_flip()
11675 if (crtc_state && INTEL_INFO(dev)->gen >= 9 && in intel_plane_atomic_calc_changes()
11771 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && in intel_plane_atomic_calc_changes()
11878 if (INTEL_INFO(dev)->gen >= 9) { in intel_crtc_atomic_check()
11963 else if (INTEL_INFO(dev)->gen >= 5) in compute_baseline_pipe_bpp()
12536 if (INTEL_INFO(dev)->gen < 8) { in intel_pipe_config_compare()
12560 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || in intel_pipe_config_compare()
12583 if (INTEL_INFO(dev)->gen < 4) in intel_pipe_config_compare()
12619 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) in intel_pipe_config_compare()
12643 if (INTEL_INFO(dev)->gen < 9) in check_wm_state()
13467 INTEL_INFO(dev)->cursor_needs_physical) { in intel_prepare_plane_fb()
13502 !INTEL_INFO(dev)->cursor_needs_physical) { in intel_cleanup_plane_fb()
13550 if (INTEL_INFO(plane->dev)->gen >= 9) { in intel_check_primary_plane()
13623 else if (INTEL_INFO(dev)->gen >= 9) in intel_begin_crtc_commit()
13683 if (INTEL_INFO(dev)->gen >= 9) { in intel_primary_plane_create()
13693 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) in intel_primary_plane_create()
13696 if (INTEL_INFO(dev)->gen >= 9) { in intel_primary_plane_create()
13699 } else if (INTEL_INFO(dev)->gen >= 4) { in intel_primary_plane_create()
13712 if (INTEL_INFO(dev)->gen >= 4) in intel_primary_plane_create()
13726 if (INTEL_INFO(dev)->gen >= 9) in intel_create_rotation_property()
13821 else if (!INTEL_INFO(dev)->cursor_needs_physical) in intel_commit_cursor_plane()
13864 if (INTEL_INFO(dev)->gen >= 4) { in intel_cursor_plane_create()
13876 if (INTEL_INFO(dev)->gen >=9) in intel_cursor_plane_create()
13921 if (INTEL_INFO(dev)->gen >= 9) { in intel_crtc_init()
13956 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { in intel_crtc_init()
14056 if (INTEL_INFO(dev)->gen >= 9) in intel_crt_present()
14292 u32 gen = INTEL_INFO(dev)->gen; in intel_fb_pitch_limit()
14349 if (INTEL_INFO(dev)->gen < 9) { in intel_framebuffer_init()
14396 if (INTEL_INFO(dev)->gen > 3) { in intel_framebuffer_init()
14403 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) { in intel_framebuffer_init()
14412 if (INTEL_INFO(dev)->gen < 4) { in intel_framebuffer_init()
14429 if (INTEL_INFO(dev)->gen < 5) { in intel_framebuffer_init()
14512 if (INTEL_INFO(dev)->gen >= 9) { in intel_init_display()
14648 switch (INTEL_INFO(dev)->gen) { in intel_init_display()
14897 if (INTEL_INFO(dev)->num_pipes == 0) in intel_modeset_init()
14946 INTEL_INFO(dev)->num_pipes, in intel_modeset_init()
14947 INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); in intel_modeset_init()
15030 if (INTEL_INFO(dev)->num_pipes == 1) in intel_check_plane_mapping()
15082 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { in intel_sanitize_crtc()
15605 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; in intel_modeset_vga_set_state()
15686 if (INTEL_INFO(dev)->num_pipes == 0) in intel_display_capture_error_state()
15709 if (INTEL_INFO(dev)->gen <= 3) { in intel_display_capture_error_state()
15713 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) in intel_display_capture_error_state()
15715 if (INTEL_INFO(dev)->gen >= 4) { in intel_display_capture_error_state()
15726 error->num_transcoders = INTEL_INFO(dev)->num_pipes; in intel_display_capture_error_state()
15766 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); in intel_display_print_error_state()
15780 if (INTEL_INFO(dev)->gen <= 3) { in intel_display_print_error_state()
15784 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) in intel_display_print_error_state()
15786 if (INTEL_INFO(dev)->gen >= 4) { in intel_display_print_error_state()