Lines Matching refs:DSPCNTR
1376 val = I915_READ(DSPCNTR(plane)); in assert_plane()
1394 u32 val = I915_READ(DSPCNTR(pipe)); in assert_planes_disabled()
1403 u32 val = I915_READ(DSPCNTR(i)); in assert_planes_disabled()
2698 u32 reg = DSPCNTR(plane); in i9xx_update_primary_plane()
2828 u32 reg = DSPCNTR(plane); in ironlake_update_primary_plane()
8043 val = I915_READ(DSPCNTR(plane)); in i9xx_get_initial_plane_config()
9204 val = I915_READ(DSPCNTR(pipe)); in ironlake_get_initial_plane_config()
11238 reg = DSPCNTR(intel_crtc->plane); in ilk_do_mmio_flip()
15033 val = I915_READ(DSPCNTR(!crtc->plane)); in intel_check_plane_mapping()
15243 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; in primary_get_hw_state()
15707 error->plane[i].control = I915_READ(DSPCNTR(i)); in intel_display_capture_error_state()