Lines Matching refs:temp
612 u32 temp, i, rx_ctl_val; in hsw_fdi_link_train() local
675 temp = I915_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
676 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); in hsw_fdi_link_train()
677 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); in hsw_fdi_link_train()
683 temp = I915_READ(DP_TP_STATUS(PORT_E)); in hsw_fdi_link_train()
684 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { in hsw_fdi_link_train()
697 temp = I915_READ(DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
698 temp &= ~DDI_BUF_CTL_ENABLE; in hsw_fdi_link_train()
699 I915_WRITE(DDI_BUF_CTL(PORT_E), temp); in hsw_fdi_link_train()
703 temp = I915_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
704 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); in hsw_fdi_link_train()
705 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; in hsw_fdi_link_train()
706 I915_WRITE(DP_TP_CTL(PORT_E), temp); in hsw_fdi_link_train()
716 temp = I915_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
717 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); in hsw_fdi_link_train()
718 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); in hsw_fdi_link_train()
719 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); in hsw_fdi_link_train()
1810 uint32_t temp; in intel_ddi_set_pipe_settings() local
1813 temp = TRANS_MSA_SYNC_CLK; in intel_ddi_set_pipe_settings()
1816 temp |= TRANS_MSA_6_BPC; in intel_ddi_set_pipe_settings()
1819 temp |= TRANS_MSA_8_BPC; in intel_ddi_set_pipe_settings()
1822 temp |= TRANS_MSA_10_BPC; in intel_ddi_set_pipe_settings()
1825 temp |= TRANS_MSA_12_BPC; in intel_ddi_set_pipe_settings()
1830 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); in intel_ddi_set_pipe_settings()
1840 uint32_t temp; in intel_ddi_set_vc_payload_alloc() local
1841 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); in intel_ddi_set_vc_payload_alloc()
1843 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; in intel_ddi_set_vc_payload_alloc()
1845 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; in intel_ddi_set_vc_payload_alloc()
1846 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); in intel_ddi_set_vc_payload_alloc()
1860 uint32_t temp; in intel_ddi_enable_transcoder_func() local
1863 temp = TRANS_DDI_FUNC_ENABLE; in intel_ddi_enable_transcoder_func()
1864 temp |= TRANS_DDI_SELECT_PORT(port); in intel_ddi_enable_transcoder_func()
1868 temp |= TRANS_DDI_BPC_6; in intel_ddi_enable_transcoder_func()
1871 temp |= TRANS_DDI_BPC_8; in intel_ddi_enable_transcoder_func()
1874 temp |= TRANS_DDI_BPC_10; in intel_ddi_enable_transcoder_func()
1877 temp |= TRANS_DDI_BPC_12; in intel_ddi_enable_transcoder_func()
1884 temp |= TRANS_DDI_PVSYNC; in intel_ddi_enable_transcoder_func()
1886 temp |= TRANS_DDI_PHSYNC; in intel_ddi_enable_transcoder_func()
1898 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; in intel_ddi_enable_transcoder_func()
1900 temp |= TRANS_DDI_EDP_INPUT_A_ON; in intel_ddi_enable_transcoder_func()
1903 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; in intel_ddi_enable_transcoder_func()
1906 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; in intel_ddi_enable_transcoder_func()
1916 temp |= TRANS_DDI_MODE_SELECT_HDMI; in intel_ddi_enable_transcoder_func()
1918 temp |= TRANS_DDI_MODE_SELECT_DVI; in intel_ddi_enable_transcoder_func()
1921 temp |= TRANS_DDI_MODE_SELECT_FDI; in intel_ddi_enable_transcoder_func()
1922 temp |= (intel_crtc->config->fdi_lanes - 1) << 1; in intel_ddi_enable_transcoder_func()
1929 temp |= TRANS_DDI_MODE_SELECT_DP_MST; in intel_ddi_enable_transcoder_func()
1931 temp |= TRANS_DDI_MODE_SELECT_DP_SST; in intel_ddi_enable_transcoder_func()
1933 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); in intel_ddi_enable_transcoder_func()
1938 temp |= TRANS_DDI_MODE_SELECT_DP_MST; in intel_ddi_enable_transcoder_func()
1940 temp |= TRANS_DDI_MODE_SELECT_DP_SST; in intel_ddi_enable_transcoder_func()
1942 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); in intel_ddi_enable_transcoder_func()
1948 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); in intel_ddi_enable_transcoder_func()
2812 uint32_t temp; in bxt_ddi_pll_enable() local
2815 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); in bxt_ddi_pll_enable()
2816 temp &= ~PORT_PLL_REF_SEL; in bxt_ddi_pll_enable()
2818 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); in bxt_ddi_pll_enable()
2821 temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); in bxt_ddi_pll_enable()
2822 temp &= ~PORT_PLL_10BIT_CLK_ENABLE; in bxt_ddi_pll_enable()
2823 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); in bxt_ddi_pll_enable()
2826 temp = I915_READ(BXT_PORT_PLL_EBB_0(port)); in bxt_ddi_pll_enable()
2827 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK); in bxt_ddi_pll_enable()
2828 temp |= pll->config.hw_state.ebb0; in bxt_ddi_pll_enable()
2829 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp); in bxt_ddi_pll_enable()
2832 temp = I915_READ(BXT_PORT_PLL(port, 0)); in bxt_ddi_pll_enable()
2833 temp &= ~PORT_PLL_M2_MASK; in bxt_ddi_pll_enable()
2834 temp |= pll->config.hw_state.pll0; in bxt_ddi_pll_enable()
2835 I915_WRITE(BXT_PORT_PLL(port, 0), temp); in bxt_ddi_pll_enable()
2838 temp = I915_READ(BXT_PORT_PLL(port, 1)); in bxt_ddi_pll_enable()
2839 temp &= ~PORT_PLL_N_MASK; in bxt_ddi_pll_enable()
2840 temp |= pll->config.hw_state.pll1; in bxt_ddi_pll_enable()
2841 I915_WRITE(BXT_PORT_PLL(port, 1), temp); in bxt_ddi_pll_enable()
2844 temp = I915_READ(BXT_PORT_PLL(port, 2)); in bxt_ddi_pll_enable()
2845 temp &= ~PORT_PLL_M2_FRAC_MASK; in bxt_ddi_pll_enable()
2846 temp |= pll->config.hw_state.pll2; in bxt_ddi_pll_enable()
2847 I915_WRITE(BXT_PORT_PLL(port, 2), temp); in bxt_ddi_pll_enable()
2850 temp = I915_READ(BXT_PORT_PLL(port, 3)); in bxt_ddi_pll_enable()
2851 temp &= ~PORT_PLL_M2_FRAC_ENABLE; in bxt_ddi_pll_enable()
2852 temp |= pll->config.hw_state.pll3; in bxt_ddi_pll_enable()
2853 I915_WRITE(BXT_PORT_PLL(port, 3), temp); in bxt_ddi_pll_enable()
2856 temp = I915_READ(BXT_PORT_PLL(port, 6)); in bxt_ddi_pll_enable()
2857 temp &= ~PORT_PLL_PROP_COEFF_MASK; in bxt_ddi_pll_enable()
2858 temp &= ~PORT_PLL_INT_COEFF_MASK; in bxt_ddi_pll_enable()
2859 temp &= ~PORT_PLL_GAIN_CTL_MASK; in bxt_ddi_pll_enable()
2860 temp |= pll->config.hw_state.pll6; in bxt_ddi_pll_enable()
2861 I915_WRITE(BXT_PORT_PLL(port, 6), temp); in bxt_ddi_pll_enable()
2864 temp = I915_READ(BXT_PORT_PLL(port, 8)); in bxt_ddi_pll_enable()
2865 temp &= ~PORT_PLL_TARGET_CNT_MASK; in bxt_ddi_pll_enable()
2866 temp |= pll->config.hw_state.pll8; in bxt_ddi_pll_enable()
2867 I915_WRITE(BXT_PORT_PLL(port, 8), temp); in bxt_ddi_pll_enable()
2869 temp = I915_READ(BXT_PORT_PLL(port, 9)); in bxt_ddi_pll_enable()
2870 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK; in bxt_ddi_pll_enable()
2871 temp |= pll->config.hw_state.pll9; in bxt_ddi_pll_enable()
2872 I915_WRITE(BXT_PORT_PLL(port, 9), temp); in bxt_ddi_pll_enable()
2874 temp = I915_READ(BXT_PORT_PLL(port, 10)); in bxt_ddi_pll_enable()
2875 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H; in bxt_ddi_pll_enable()
2876 temp &= ~PORT_PLL_DCO_AMP_MASK; in bxt_ddi_pll_enable()
2877 temp |= pll->config.hw_state.pll10; in bxt_ddi_pll_enable()
2878 I915_WRITE(BXT_PORT_PLL(port, 10), temp); in bxt_ddi_pll_enable()
2881 temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); in bxt_ddi_pll_enable()
2882 temp |= PORT_PLL_RECALIBRATE; in bxt_ddi_pll_enable()
2883 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); in bxt_ddi_pll_enable()
2884 temp &= ~PORT_PLL_10BIT_CLK_ENABLE; in bxt_ddi_pll_enable()
2885 temp |= pll->config.hw_state.ebb4; in bxt_ddi_pll_enable()
2886 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); in bxt_ddi_pll_enable()
2889 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); in bxt_ddi_pll_enable()
2890 temp |= PORT_PLL_ENABLE; in bxt_ddi_pll_enable()
2891 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); in bxt_ddi_pll_enable()
2902 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); in bxt_ddi_pll_enable()
2903 temp &= ~LANE_STAGGER_MASK; in bxt_ddi_pll_enable()
2904 temp &= ~LANESTAGGER_STRAP_OVRD; in bxt_ddi_pll_enable()
2905 temp |= pll->config.hw_state.pcsdw12; in bxt_ddi_pll_enable()
2906 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp); in bxt_ddi_pll_enable()
2913 uint32_t temp; in bxt_ddi_pll_disable() local
2915 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); in bxt_ddi_pll_disable()
2916 temp &= ~PORT_PLL_ENABLE; in bxt_ddi_pll_disable()
2917 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); in bxt_ddi_pll_disable()
3117 u32 temp, flags = 0; in intel_ddi_get_config() local
3119 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); in intel_ddi_get_config()
3120 if (temp & TRANS_DDI_PHSYNC) in intel_ddi_get_config()
3124 if (temp & TRANS_DDI_PVSYNC) in intel_ddi_get_config()
3131 switch (temp & TRANS_DDI_BPC_MASK) { in intel_ddi_get_config()
3148 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { in intel_ddi_get_config()
3163 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; in intel_ddi_get_config()
3171 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); in intel_ddi_get_config()
3172 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) in intel_ddi_get_config()