1035 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)  in ddi_dotclock_get()  argument
1039 	if (pipe_config->has_pch_encoder)  in ddi_dotclock_get()
1040 		dotclock = intel_dotclock_calculate(pipe_config->port_clock,  in ddi_dotclock_get()
1041 						    &pipe_config->fdi_m_n);  in ddi_dotclock_get()
1042 	else if (pipe_config->has_dp_encoder)  in ddi_dotclock_get()
1043 		dotclock = intel_dotclock_calculate(pipe_config->port_clock,  in ddi_dotclock_get()
1044 						    &pipe_config->dp_m_n);  in ddi_dotclock_get()
1045 	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)  in ddi_dotclock_get()
1046 		dotclock = pipe_config->port_clock * 2 / 3;  in ddi_dotclock_get()
1048 		dotclock = pipe_config->port_clock;  in ddi_dotclock_get()
1050 	if (pipe_config->pixel_multiplier)  in ddi_dotclock_get()
1051 		dotclock /= pipe_config->pixel_multiplier;  in ddi_dotclock_get()
1053 	pipe_config->base.adjusted_mode.crtc_clock = dotclock;  in ddi_dotclock_get()
1057 				struct intel_crtc_state *pipe_config)  in skl_ddi_clock_get()  argument
1063 	dpll = pipe_config->ddi_pll_sel;  in skl_ddi_clock_get()
1099 	pipe_config->port_clock = link_clock;  in skl_ddi_clock_get()
1101 	ddi_dotclock_get(pipe_config);  in skl_ddi_clock_get()
1105 			      struct intel_crtc_state *pipe_config)  in hsw_ddi_clock_get()  argument
1111 	val = pipe_config->ddi_pll_sel;  in hsw_ddi_clock_get()
1146 	pipe_config->port_clock = link_clock * 2;  in hsw_ddi_clock_get()
1148 	ddi_dotclock_get(pipe_config);  in hsw_ddi_clock_get()
1177 				struct intel_crtc_state *pipe_config)  in bxt_ddi_clock_get()  argument
1183 	pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);  in bxt_ddi_clock_get()
1185 	ddi_dotclock_get(pipe_config);  in bxt_ddi_clock_get()
1189 			 struct intel_crtc_state *pipe_config)  in intel_ddi_clock_get()  argument
1194 		hsw_ddi_clock_get(encoder, pipe_config);  in intel_ddi_clock_get()
1196 		skl_ddi_clock_get(encoder, pipe_config);  in intel_ddi_clock_get()
1198 		bxt_ddi_clock_get(encoder, pipe_config);  in intel_ddi_clock_get()
3111 			  struct intel_crtc_state *pipe_config)  in intel_ddi_get_config()  argument
3115 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;  in intel_ddi_get_config()
3129 	pipe_config->base.adjusted_mode.flags |= flags;  in intel_ddi_get_config()
3133 		pipe_config->pipe_bpp = 18;  in intel_ddi_get_config()
3136 		pipe_config->pipe_bpp = 24;  in intel_ddi_get_config()
3139 		pipe_config->pipe_bpp = 30;  in intel_ddi_get_config()
3142 		pipe_config->pipe_bpp = 36;  in intel_ddi_get_config()
3150 		pipe_config->has_hdmi_sink = true;  in intel_ddi_get_config()
3154 			pipe_config->has_infoframe = true;  in intel_ddi_get_config()
3161 		pipe_config->has_dp_encoder = true;  in intel_ddi_get_config()
3162 		pipe_config->lane_count =  in intel_ddi_get_config()
3164 		intel_dp_get_m_n(intel_crtc, pipe_config);  in intel_ddi_get_config()
3173 			pipe_config->has_audio = true;  in intel_ddi_get_config()
3177 	    pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {  in intel_ddi_get_config()
3192 			      pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);  in intel_ddi_get_config()
3193 		dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;  in intel_ddi_get_config()
3196 	intel_ddi_clock_get(encoder, pipe_config);  in intel_ddi_get_config()
3200 				     struct intel_crtc_state *pipe_config)  in intel_ddi_compute_config()  argument
3208 		pipe_config->cpu_transcoder = TRANSCODER_EDP;  in intel_ddi_compute_config()
3211 		return intel_hdmi_compute_config(encoder, pipe_config);  in intel_ddi_compute_config()
3213 		return intel_dp_compute_config(encoder, pipe_config);  in intel_ddi_compute_config()