980 	uint32_t p0, p1, p2, dco_freq;  in skl_calc_wrpll_link()  local
989 	p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;  in skl_calc_wrpll_link()
1012 	switch (p2) {  in skl_calc_wrpll_link()
1014 		p2 = 5;  in skl_calc_wrpll_link()
1017 		p2 = 2;  in skl_calc_wrpll_link()
1020 		p2 = 3;  in skl_calc_wrpll_link()
1023 		p2 = 1;  in skl_calc_wrpll_link()
1032 	return dco_freq / (p0 * p1 * p2 * 5);  in skl_calc_wrpll_link()
1171 	clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;  in bxt_calc_pll_link()
1364 				      unsigned int *p2 /* out */)  in skl_wrpll_get_multipliers()  argument
1373 			*p2 = half;  in skl_wrpll_get_multipliers()
1377 			*p2 = 2;  in skl_wrpll_get_multipliers()
1381 			*p2 = 2;  in skl_wrpll_get_multipliers()
1385 			*p2 = 2;  in skl_wrpll_get_multipliers()
1390 		*p2 = p / 3;  in skl_wrpll_get_multipliers()
1394 		*p2 = 1;  in skl_wrpll_get_multipliers()
1398 		*p2 = 5;  in skl_wrpll_get_multipliers()
1402 		*p2 = 3;  in skl_wrpll_get_multipliers()
1406 		*p2 = 5;  in skl_wrpll_get_multipliers()
1423 				      uint32_t p0, uint32_t p1, uint32_t p2)  in skl_wrpll_params_populate()  argument
1455 	switch (p2) {  in skl_wrpll_params_populate()
1475 	dco_freq = p0 * p1 * p2 * afe_clock;  in skl_wrpll_params_populate()
1510 	unsigned int p0, p1, p2;  in skl_ddi_calculate_wrpll()  local
1552 	p0 = p1 = p2 = 0;  in skl_ddi_calculate_wrpll()
1553 	skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);  in skl_ddi_calculate_wrpll()
1555 				  p0, p1, p2);  in skl_ddi_calculate_wrpll()
1635 	uint32_t p2;  member
1680 		clk_div.p2 = best_clock.p2;  in bxt_ddi_pll_select()
1699 		vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;  in bxt_ddi_pll_select()
1738 		PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);  in bxt_ddi_pll_select()