Lines Matching refs:p0
980 uint32_t p0, p1, p2, dco_freq; in skl_calc_wrpll_link() local
988 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK; in skl_calc_wrpll_link()
997 switch (p0) { in skl_calc_wrpll_link()
999 p0 = 1; in skl_calc_wrpll_link()
1002 p0 = 2; in skl_calc_wrpll_link()
1005 p0 = 3; in skl_calc_wrpll_link()
1008 p0 = 7; in skl_calc_wrpll_link()
1032 return dco_freq / (p0 * p1 * p2 * 5); in skl_calc_wrpll_link()
1362 unsigned int *p0 /* out */, in skl_wrpll_get_multipliers() argument
1371 *p0 = 2; in skl_wrpll_get_multipliers()
1375 *p0 = 2; in skl_wrpll_get_multipliers()
1379 *p0 = 3; in skl_wrpll_get_multipliers()
1383 *p0 = 7; in skl_wrpll_get_multipliers()
1388 *p0 = 3; in skl_wrpll_get_multipliers()
1392 *p0 = p; in skl_wrpll_get_multipliers()
1396 *p0 = 3; in skl_wrpll_get_multipliers()
1400 *p0 = 7; in skl_wrpll_get_multipliers()
1404 *p0 = 7; in skl_wrpll_get_multipliers()
1423 uint32_t p0, uint32_t p1, uint32_t p2) in skl_wrpll_params_populate() argument
1438 switch (p0) { in skl_wrpll_params_populate()
1475 dco_freq = p0 * p1 * p2 * afe_clock; in skl_wrpll_params_populate()
1510 unsigned int p0, p1, p2; in skl_ddi_calculate_wrpll() local
1552 p0 = p1 = p2 = 0; in skl_ddi_calculate_wrpll()
1553 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2); in skl_ddi_calculate_wrpll()
1555 p0, p1, p2); in skl_ddi_calculate_wrpll()