Lines Matching refs:clk_div
1659 struct bxt_clk_div clk_div = {0}; in bxt_ddi_pll_select() local
1679 clk_div.p1 = best_clock.p1; in bxt_ddi_pll_select()
1680 clk_div.p2 = best_clock.p2; in bxt_ddi_pll_select()
1682 clk_div.n = best_clock.n; in bxt_ddi_pll_select()
1683 clk_div.m2_int = best_clock.m2 >> 22; in bxt_ddi_pll_select()
1684 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1); in bxt_ddi_pll_select()
1685 clk_div.m2_frac_en = clk_div.m2_frac != 0; in bxt_ddi_pll_select()
1692 clk_div = bxt_dp_clk_val[0]; in bxt_ddi_pll_select()
1695 clk_div = bxt_dp_clk_val[i]; in bxt_ddi_pll_select()
1699 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; in bxt_ddi_pll_select()
1738 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2); in bxt_ddi_pll_select()
1739 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int; in bxt_ddi_pll_select()
1740 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n); in bxt_ddi_pll_select()
1741 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac; in bxt_ddi_pll_select()
1743 if (clk_div.m2_frac_en) in bxt_ddi_pll_select()