Lines Matching refs:pipe_config
114 struct intel_crtc_state *pipe_config) in intel_crt_get_config() argument
119 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); in intel_crt_get_config()
121 dotclock = pipe_config->port_clock; in intel_crt_get_config()
124 ironlake_check_encoder_dotclock(pipe_config, dotclock); in intel_crt_get_config()
126 pipe_config->base.adjusted_mode.crtc_clock = dotclock; in intel_crt_get_config()
130 struct intel_crtc_state *pipe_config) in hsw_crt_get_config() argument
132 intel_ddi_get_config(encoder, pipe_config); in hsw_crt_get_config()
134 pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | in hsw_crt_get_config()
138 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); in hsw_crt_get_config()
243 struct intel_crtc_state *pipe_config) in intel_crt_compute_config() argument
248 pipe_config->has_pch_encoder = true; in intel_crt_compute_config()
252 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { in intel_crt_compute_config()
257 pipe_config->pipe_bpp = 24; in intel_crt_compute_config()
262 pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL; in intel_crt_compute_config()
263 pipe_config->port_clock = 135000 * 2; in intel_crt_compute_config()
265 pipe_config->dpll_hw_state.wrpll = 0; in intel_crt_compute_config()
266 pipe_config->dpll_hw_state.spll = in intel_crt_compute_config()