Lines Matching refs:u8
34 u8 signature[20]; /**< Always starts with 'VBT$' */
38 u8 vbt_checksum;
39 u8 reserved0;
45 u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */
53 u8 type; /* 0 == desktop, 1 == mobile */
54 u8 relstage;
55 u8 chipset;
56 u8 lvds_present:1;
57 u8 tv_present:1;
58 u8 rsvd2:6; /* finish byte */
59 u8 rsvd3[4];
60 u8 signon[155];
61 u8 copyright[61];
63 u8 dos_boot_mode;
64 u8 bandwidth_percent;
65 u8 rsvd4; /* popup memory size */
66 u8 resize_pci_bios;
67 u8 rsvd5; /* is crt already on ddc2 */
113 u8 panel_fitting:2;
114 u8 flexaim:1;
115 u8 msg_enable:1;
116 u8 clear_screen:3;
117 u8 color_flip:1;
120 u8 download_ext_vbt:1;
121 u8 enable_ssc:1;
122 u8 ssc_freq:1;
123 u8 enable_lfp_on_override:1;
124 u8 disable_ssc_ddt:1;
125 u8 rsvd7:1;
126 u8 display_clock_mode:1;
127 u8 rsvd8:1; /* finish byte */
130 u8 disable_smooth_vision:1;
131 u8 single_dvi:1;
132 u8 rsvd9:1;
133 u8 fdi_rx_polarity_inverted:1;
134 u8 rsvd10:4; /* finish byte */
137 u8 legacy_monitor_detect;
140 u8 int_crt_support:1;
141 u8 int_tv_support:1;
142 u8 int_efp_support:1;
143 u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */
144 u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */
145 u8 rsvd11:3; /* finish byte */
214 u8 device_id[10]; /* ascii string */
216 u8 dvo_port; /* See Device_PORT_* above */
217 u8 i2c_pin;
218 u8 slave_addr;
219 u8 ddc_pin;
221 u8 dvo_cfg; /* See DEVICE_CFG_* above */
222 u8 dvo2_port;
223 u8 i2c2_pin;
224 u8 slave2_addr;
225 u8 ddc2_pin;
226 u8 capabilities;
227 u8 dvo_wiring;/* See DEVICE_WIRE_* above */
228 u8 dvo2_wiring;
230 u8 dvo_function;
243 u8 not_common1[12];
244 u8 dvo_port;
245 u8 not_common2[2];
246 u8 ddc_pin;
248 u8 obsolete;
249 u8 flags_1;
250 u8 not_common3[13];
251 u8 iboost_level;
260 u8 raw[33];
270 u8 crt_ddc_gmbus_pin;
273 u8 dpms_acpi:1;
274 u8 skip_boot_crt_detect:1;
275 u8 dpms_aim:1;
276 u8 rsvd1:5; /* finish byte */
279 u8 boot_display[2];
280 u8 child_dev_size;
300 u8 panel_type;
301 u8 rsvd1;
303 u8 pfit_mode:2;
304 u8 pfit_text_mode_enhanced:1;
305 u8 pfit_gfx_mode_enhanced:1;
306 u8 pfit_ratio_auto:1;
307 u8 pixel_dither:1;
308 u8 lvds_edid:1;
309 u8 rsvd2:1;
310 u8 rsvd4;
328 u8 fp_table_size;
330 u8 dvo_table_size;
332 u8 pnp_table_size;
336 u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
359 u8 hactive_lo;
360 u8 hblank_lo;
361 u8 hblank_hi:4;
362 u8 hactive_hi:4;
363 u8 vactive_lo;
364 u8 vblank_lo;
365 u8 vblank_hi:4;
366 u8 vactive_hi:4;
367 u8 hsync_off_lo;
368 u8 hsync_pulse_width;
369 u8 vsync_pulse_width:4;
370 u8 vsync_off:4;
371 u8 rsvd0:6;
372 u8 hsync_off_hi:2;
373 u8 h_image;
374 u8 v_image;
375 u8 max_hv;
376 u8 h_border;
377 u8 v_border;
378 u8 rsvd1:3;
379 u8 digital:2;
380 u8 vsync_positive:1;
381 u8 hsync_positive:1;
382 u8 rsvd2:1;
389 u8 mfg_week;
390 u8 mfg_year;
407 u8 type:2;
408 u8 active_low_pwm:1;
409 u8 obsolete1:5;
411 u8 min_brightness;
412 u8 obsolete2;
413 u8 obsolete3;
417 u8 entry_size;
419 u8 level[16];
431 u8 aimdb_id;
437 u8 fp_timing_size;
439 u8 dvo_timing_size;
441 u8 text_fitting_size;
443 u8 graphics_fitting_size;
452 u8 panel_backlight;
453 u8 h40_set_panel_type;
454 u8 panel_type;
455 u8 ssc_clk_freq;
458 u8 sclalarcoeff_tab_row_num;
459 u8 sclalarcoeff_tab_row_size;
460 u8 coefficient[8];
461 u8 panel_misc_bits_1;
462 u8 panel_misc_bits_2;
463 u8 panel_misc_bits_3;
464 u8 panel_misc_bits_4;
474 u8 boot_dev_algorithm:1;
475 u8 block_display_switch:1;
476 u8 allow_display_switch:1;
477 u8 hotplug_dvo:1;
478 u8 dual_view_zoom:1;
479 u8 int15h_hook:1;
480 u8 sprite_in_clone:1;
481 u8 primary_lfp_id:1;
485 u8 boot_mode_bpp;
486 u8 boot_mode_refresh;
503 u8 static_display:1;
504 u8 reserved2:7;
507 u8 legacy_crt_max_refresh;
509 u8 hdmi_termination;
510 u8 custom_vbt_version;
553 u8 rate:4;
554 u8 lanes:4;
555 u8 preemphasis:4;
556 u8 vswing:4;
573 u8 full_link:1;
574 u8 require_aux_to_wakeup:1;
575 u8 feature_bits_rsvd:6;
578 u8 idle_frames:4;
579 u8 lines_to_wait:3;
580 u8 wait_times_rsvd:1;
839 u8 rsvd5;
847 u8 byte_clk_sel:2;
849 u8 rsvd6:6;
880 u8 tclk_miss;
881 u8 tclk_post;
882 u8 rsvd12;
883 u8 tclk_pre;
884 u8 tclk_prepare;
885 u8 tclk_settle;
886 u8 tclk_term_enable;
887 u8 tclk_trail;
889 u8 rsvd13;
890 u8 td_term_enable;
891 u8 teot;
892 u8 ths_exit;
893 u8 ths_prepare;
895 u8 rsvd14;
896 u8 ths_settle;
897 u8 ths_skip;
898 u8 ths_trail;
899 u8 tinit;
900 u8 tlpx;
901 u8 rsvd15[3];
904 u8 panel_enable;
905 u8 bl_enable;
906 u8 pwm_enable;
907 u8 reset_r_n;
908 u8 pwr_down_r;
909 u8 stdby_r_n;
937 u8 version;
938 u8 data[0];