Lines Matching defs:mipi_config
793 struct mipi_config { struct
794 u16 panel_id;
797 u32 enable_dithering:1;
798 u32 rsvd1:1;
799 u32 is_bridge:1;
801 u32 panel_arch_type:2;
802 u32 is_cmd_mode:1;
807 u32 video_transfer_mode:2;
809 u32 cabc_supported:1;
810 u32 pwm_blc:1;
817 u32 videomode_color_format:4;
824 u32 rotation:2;
825 u32 bta_enabled:1;
826 u32 rsvd2:15;
832 u16 dual_link:2;
833 u16 lane_cnt:2;
834 u16 pixel_overlap:3;
835 u16 rsvd3:9;
837 u16 rsvd4;
839 u8 rsvd5;
840 u32 target_burst_mode_freq;
841 u32 dsi_ddr_clk;
842 u32 bridge_ref_clk;
847 u8 byte_clk_sel:2;
849 u8 rsvd6:6;
852 u16 dphy_param_valid:1;
853 u16 eot_pkt_disabled:1;
854 u16 enable_clk_stop:1;
855 u16 rsvd7:13;
857 u32 hs_tx_timeout;
858 u32 lp_rx_timeout;
859 u32 turn_around_timeout;
860 u32 device_reset_timer;
861 u32 master_init_timer;
862 u32 dbi_bw_timer;
863 u32 lp_byte_clk_val;
866 u32 prepare_cnt:6;
867 u32 rsvd8:2;
868 u32 clk_zero_cnt:8;
869 u32 trail_cnt:5;
870 u32 rsvd9:3;
871 u32 exit_zero_cnt:6;
872 u32 rsvd10:2;
874 u32 clk_lane_switch_cnt;
875 u32 hl_switch_cnt;
877 u32 rsvd11[6];
880 u8 tclk_miss;
881 u8 tclk_post;
882 u8 rsvd12;
883 u8 tclk_pre;
884 u8 tclk_prepare;
885 u8 tclk_settle;
886 u8 tclk_term_enable;
887 u8 tclk_trail;
888 u16 tclk_prepare_clkzero;
889 u8 rsvd13;
890 u8 td_term_enable;
914 * 6 * bdb_mipi_config, followed by 6 pps data argument
928 struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; argument