40 	struct drm_i915_private *dev_priv = dev->dev_private;  in calc_residency()  local
48 	intel_runtime_pm_get(dev_priv);  in calc_residency()
53 		div = dev_priv->czclk_freq;  in calc_residency()
65 	intel_runtime_pm_put(dev_priv);  in calc_residency()
169 	struct drm_i915_private *dev_priv = drm_dev->dev_private;  in i915_l3_read()  local
185 	if (dev_priv->l3_parity.remap_info[slice])  in i915_l3_read()
187 		       dev_priv->l3_parity.remap_info[slice] + (offset/4),  in i915_l3_read()
205 	struct drm_i915_private *dev_priv = drm_dev->dev_private;  in i915_l3_write()  local
222 	if (!dev_priv->l3_parity.remap_info[slice]) {  in i915_l3_write()
242 		dev_priv->l3_parity.remap_info[slice] = temp;  in i915_l3_write()
244 	memcpy(dev_priv->l3_parity.remap_info[slice] + (offset/4), buf, count);  in i915_l3_write()
247 	list_for_each_entry(ctx, &dev_priv->context_list, link)  in i915_l3_write()
278 	struct drm_i915_private *dev_priv = dev->dev_private;  in gt_act_freq_mhz_show()  local
281 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_act_freq_mhz_show()
283 	intel_runtime_pm_get(dev_priv);  in gt_act_freq_mhz_show()
285 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_act_freq_mhz_show()
286 	if (IS_VALLEYVIEW(dev_priv->dev)) {  in gt_act_freq_mhz_show()
288 		freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);  in gt_act_freq_mhz_show()
289 		ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);  in gt_act_freq_mhz_show()
292 		if (IS_GEN9(dev_priv))  in gt_act_freq_mhz_show()
294 		else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))  in gt_act_freq_mhz_show()
298 		ret = intel_gpu_freq(dev_priv, ret);  in gt_act_freq_mhz_show()
300 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_act_freq_mhz_show()
302 	intel_runtime_pm_put(dev_priv);  in gt_act_freq_mhz_show()
312 	struct drm_i915_private *dev_priv = dev->dev_private;  in gt_cur_freq_mhz_show()  local
315 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_cur_freq_mhz_show()
317 	intel_runtime_pm_get(dev_priv);  in gt_cur_freq_mhz_show()
319 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_cur_freq_mhz_show()
320 	ret = intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq);  in gt_cur_freq_mhz_show()
321 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_cur_freq_mhz_show()
323 	intel_runtime_pm_put(dev_priv);  in gt_cur_freq_mhz_show()
333 	struct drm_i915_private *dev_priv = dev->dev_private;  in vlv_rpe_freq_mhz_show()  local
337 			intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));  in vlv_rpe_freq_mhz_show()
344 	struct drm_i915_private *dev_priv = dev->dev_private;  in gt_max_freq_mhz_show()  local
347 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_max_freq_mhz_show()
349 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_max_freq_mhz_show()
350 	ret = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);  in gt_max_freq_mhz_show()
351 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_max_freq_mhz_show()
362 	struct drm_i915_private *dev_priv = dev->dev_private;  in gt_max_freq_mhz_store()  local
370 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_max_freq_mhz_store()
372 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_max_freq_mhz_store()
374 	val = intel_freq_opcode(dev_priv, val);  in gt_max_freq_mhz_store()
376 	if (val < dev_priv->rps.min_freq ||  in gt_max_freq_mhz_store()
377 	    val > dev_priv->rps.max_freq ||  in gt_max_freq_mhz_store()
378 	    val < dev_priv->rps.min_freq_softlimit) {  in gt_max_freq_mhz_store()
379 		mutex_unlock(&dev_priv->rps.hw_lock);  in gt_max_freq_mhz_store()
383 	if (val > dev_priv->rps.rp0_freq)  in gt_max_freq_mhz_store()
385 			  intel_gpu_freq(dev_priv, val));  in gt_max_freq_mhz_store()
387 	dev_priv->rps.max_freq_softlimit = val;  in gt_max_freq_mhz_store()
389 	val = clamp_t(int, dev_priv->rps.cur_freq,  in gt_max_freq_mhz_store()
390 		      dev_priv->rps.min_freq_softlimit,  in gt_max_freq_mhz_store()
391 		      dev_priv->rps.max_freq_softlimit);  in gt_max_freq_mhz_store()
398 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_max_freq_mhz_store()
407 	struct drm_i915_private *dev_priv = dev->dev_private;  in gt_min_freq_mhz_show()  local
410 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_min_freq_mhz_show()
412 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_min_freq_mhz_show()
413 	ret = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);  in gt_min_freq_mhz_show()
414 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_min_freq_mhz_show()
425 	struct drm_i915_private *dev_priv = dev->dev_private;  in gt_min_freq_mhz_store()  local
433 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_min_freq_mhz_store()
435 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_min_freq_mhz_store()
437 	val = intel_freq_opcode(dev_priv, val);  in gt_min_freq_mhz_store()
439 	if (val < dev_priv->rps.min_freq ||  in gt_min_freq_mhz_store()
440 	    val > dev_priv->rps.max_freq ||  in gt_min_freq_mhz_store()
441 	    val > dev_priv->rps.max_freq_softlimit) {  in gt_min_freq_mhz_store()
442 		mutex_unlock(&dev_priv->rps.hw_lock);  in gt_min_freq_mhz_store()
446 	dev_priv->rps.min_freq_softlimit = val;  in gt_min_freq_mhz_store()
448 	val = clamp_t(int, dev_priv->rps.cur_freq,  in gt_min_freq_mhz_store()
449 		      dev_priv->rps.min_freq_softlimit,  in gt_min_freq_mhz_store()
450 		      dev_priv->rps.max_freq_softlimit);  in gt_min_freq_mhz_store()
457 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_min_freq_mhz_store()
480 	struct drm_i915_private *dev_priv = dev->dev_private;  in gt_rp_mhz_show()  local
484 		val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);  in gt_rp_mhz_show()
486 		val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);  in gt_rp_mhz_show()
488 		val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq);  in gt_rp_mhz_show()