Lines Matching refs:display_mmio_offset

2201 #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
2202 #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
2203 #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
2300 #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
2301 #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
2302 #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
2372 #define DSPCLK_GATE_D	(dev_priv->info.display_mmio_offset + 0x6200)
2512 			  dev_priv->info.display_mmio_offset + (i) * 4)
3035 	dev_priv->info.display_mmio_offset)
3211 #define PORT_HOTPLUG_EN		(dev_priv->info.display_mmio_offset + 0x61110)
3241 #define PORT_HOTPLUG_STAT	(dev_priv->info.display_mmio_offset + 0x61114)
3320 #define PORT_DFT2_G4X		(dev_priv->info.display_mmio_offset + 0x61154)
3530 #define PFIT_CONTROL	(dev_priv->info.display_mmio_offset + 0x61230)
3548 #define PFIT_PGM_RATIOS	(dev_priv->info.display_mmio_offset + 0x61234)
3560 #define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
3562 #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
3563 #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
3567 #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
3568 #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
3572 #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
3573 #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
3578 #define BLC_PWM_CTL2	(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
3601 #define BLC_PWM_CTL	(dev_priv->info.display_mmio_offset + 0x61254)
3623 #define BLC_HIST_CTL	(dev_priv->info.display_mmio_offset + 0x61260)
4466 	dev_priv->info.display_mmio_offset)
4537 #define DSPARB			(dev_priv->info.display_mmio_offset + 0x70030)
4572 #define DSPFW1			(dev_priv->info.display_mmio_offset + 0x70034)
4583 #define DSPFW2			(dev_priv->info.display_mmio_offset + 0x70038)
4599 #define DSPFW3			(dev_priv->info.display_mmio_offset + 0x7003c)
4908 	dev_priv->info.display_mmio_offset)
5012 #define SWF0(i)	(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
5013 #define SWF1(i)	(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
5014 #define SWF3(i)	(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
5017 #define _PIPEBDSL		(dev_priv->info.display_mmio_offset + 0x71000)
5018 #define _PIPEBCONF		(dev_priv->info.display_mmio_offset + 0x71008)
5019 #define _PIPEBSTAT		(dev_priv->info.display_mmio_offset + 0x71024)
5022 #define _PIPEB_FRMCOUNT_G4X	(dev_priv->info.display_mmio_offset + 0x71040)
5023 #define _PIPEB_FLIPCOUNT_G4X	(dev_priv->info.display_mmio_offset + 0x71044)
5027 #define _DSPBCNTR		(dev_priv->info.display_mmio_offset + 0x71180)
5032 #define _DSPBADDR		(dev_priv->info.display_mmio_offset + 0x71184)
5033 #define _DSPBSTRIDE		(dev_priv->info.display_mmio_offset + 0x71188)
5034 #define _DSPBPOS		(dev_priv->info.display_mmio_offset + 0x7118C)
5035 #define _DSPBSIZE		(dev_priv->info.display_mmio_offset + 0x71190)
5036 #define _DSPBSURF		(dev_priv->info.display_mmio_offset + 0x7119C)
5037 #define _DSPBTILEOFF		(dev_priv->info.display_mmio_offset + 0x711A4)
5038 #define _DSPBOFFSET		(dev_priv->info.display_mmio_offset + 0x711A4)
5039 #define _DSPBSURFLIVE		(dev_priv->info.display_mmio_offset + 0x711AC)
7024 #define G4X_AUD_VID_DID			(dev_priv->info.display_mmio_offset + 0x62020)
8146 #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
8147 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)