Lines Matching refs:dev_priv
842 #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
2147 #define GMBUS0 (dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
2166 #define GMBUS1 (dev_priv->gpio_mmio_base + 0x5104) /* command/status */
2180 #define GMBUS2 (dev_priv->gpio_mmio_base + 0x5108) /* status */
2188 #define GMBUS3 (dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
2189 #define GMBUS4 (dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
2195 #define GMBUS5 (dev_priv->gpio_mmio_base + 0x5120) /* byte index */
2201 #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
2202 #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
2203 #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
2300 #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
2301 #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
2302 #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
2372 #define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200)
2511 #define PALETTE(pipe, i) (dev_priv->info.palette_offsets[pipe] + \
2512 dev_priv->info.display_mmio_offset + (i) * 4)
2851 #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \ argument
2852 (IS_BROXTON(dev_priv) ? \
3033 #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
3034 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
3035 dev_priv->info.display_mmio_offset)
3211 #define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110)
3241 #define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114)
3320 #define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154)
3530 #define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230)
3548 #define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234)
3560 #define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
3562 #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
3563 #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
3567 #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
3568 #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
3572 #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
3573 #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
3578 #define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
3601 #define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254)
3623 #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
4464 #define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \
4465 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
4466 dev_priv->info.display_mmio_offset)
4537 #define DSPARB (dev_priv->info.display_mmio_offset + 0x70030)
4572 #define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034)
4583 #define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038)
4599 #define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c)
4906 #define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \
4907 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
4908 dev_priv->info.display_mmio_offset)
5012 #define SWF0(i) (dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
5013 #define SWF1(i) (dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
5014 #define SWF3(i) (dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
5017 #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
5018 #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
5019 #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
5022 #define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040)
5023 #define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044)
5027 #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
5032 #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
5033 #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
5034 #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
5035 #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
5036 #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
5037 #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
5038 #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
5039 #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
7024 #define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020)
7738 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
7739 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
7749 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
7750 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
7753 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
7754 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
7790 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
7791 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
7814 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
7815 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
7820 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
7821 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
7826 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
7827 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
7832 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
7833 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
7838 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
7839 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
7847 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
7848 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
7856 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
7857 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
7861 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
7862 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
7866 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
7867 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
7871 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
7872 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
7876 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
7877 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
7881 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
7882 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
7886 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
7887 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
7891 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
7892 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
7898 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
7899 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
7910 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
7911 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
7917 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
7918 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
7924 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
7925 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
7931 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
7932 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
7942 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
7943 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
7955 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
7956 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
7963 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
7964 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
7969 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
7970 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
7974 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
7975 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
7978 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
7979 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
7992 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
7993 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
8011 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
8012 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
8019 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
8020 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
8033 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
8034 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
8038 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \
8040 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \
8049 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
8050 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
8056 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
8057 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
8060 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
8061 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
8067 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
8081 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
8082 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
8101 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
8102 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
8109 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
8110 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
8116 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
8117 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
8126 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
8127 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
8133 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
8134 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
8139 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
8140 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
8146 #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
8147 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)