Lines Matching refs:VLV_DISPLAY_BASE
562 #define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100)
579 #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
580 #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
835 #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)
1727 #define VLV_DISPLAY_BASE 0x180000 macro
1728 #define VLV_MIPI_BASE VLV_DISPLAY_BASE
1730 #define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030)
1731 #define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034)
1737 #define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)
1740 #define VLV_GUNIT_CLOCK_GATE2 (VLV_DISPLAY_BASE + 0x2064)
1741 #define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)
1742 #define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)
1743 #define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
1744 #define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
1745 #define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
1746 #define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
1884 #define CHV_FUSE_GT (VLV_DISPLAY_BASE + 0x2168)
2244 #define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240)
2246 #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
2257 #define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
2486 #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500)
2489 #define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)
2491 #define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508)
2496 #define GCI_CONTROL (VLV_DISPLAY_BASE + 0x650C)
2503 #define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510)
3049 #define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)
3050 #define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090)
3064 #define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)
3065 #define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)
3071 #define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094)
3072 #define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094)
3165 #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)
3310 #define VLV_HDMIB (VLV_DISPLAY_BASE + GEN4_HDMIB)
3311 #define VLV_HDMIC (VLV_DISPLAY_BASE + GEN4_HDMIC)
3312 #define CHV_HDMID (VLV_DISPLAY_BASE + 0x6116C)
4153 #define VLV_DP_B (VLV_DISPLAY_BASE + DP_B)
4154 #define VLV_DP_C (VLV_DISPLAY_BASE + DP_C)
4155 #define CHV_DP_D (VLV_DISPLAY_BASE + DP_D)
4486 #define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028)
4507 #define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
4552 #define DSPARB2 (VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
4565 #define DSPARB3 (VLV_DISPLAY_BASE + 0x7006c) /* chv */
4610 #define DSPFW4 (VLV_DISPLAY_BASE + 0x70070)
4617 #define DSPFW5 (VLV_DISPLAY_BASE + 0x70074)
4626 #define DSPFW6 (VLV_DISPLAY_BASE + 0x70078)
4629 #define DSPFW7 (VLV_DISPLAY_BASE + 0x7007c)
4630 #define DSPFW7_CHV (VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
4639 #define DSPFW8_CHV (VLV_DISPLAY_BASE + 0x700b8)
4648 #define DSPFW9_CHV (VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
4659 #define DSPHOWM (VLV_DISPLAY_BASE + 0x70064)
4680 #define DSPHOWM1 (VLV_DISPLAY_BASE + 0x70068)
4703 #define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
4711 #define CBR1_VLV (VLV_DISPLAY_BASE + 0x70400)
5185 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
5207 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
5208 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
5209 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
5210 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
5211 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
5212 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
5213 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
5214 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
5215 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
5216 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
5218 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
5220 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
5221 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
5222 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
5223 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
5224 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
5225 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
5226 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
5227 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
5228 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
5229 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
5230 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
5231 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
5253 #define SPCSCYGOFF(sprite) (VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000)
5254 #define SPCSCCBOFF(sprite) (VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000)
5255 #define SPCSCCROFF(sprite) (VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000)
5259 #define SPCSCC01(sprite) (VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000)
5260 #define SPCSCC23(sprite) (VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000)
5261 #define SPCSCC45(sprite) (VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000)
5262 #define SPCSCC67(sprite) (VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000)
5263 #define SPCSCC8(sprite) (VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000)
5267 #define SPCSCYGICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000)
5268 #define SPCSCCBICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000)
5269 #define SPCSCCRICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000)
5273 #define SPCSCYGOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000)
5274 #define SPCSCCBOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000)
5275 #define SPCSCCROCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000)
5454 #define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400)
6245 #define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
6246 #define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
6247 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
6249 #define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
6250 #define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
6251 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
6253 #define CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
6254 #define CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
6255 #define CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
6535 #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
6536 #define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
6537 #define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
6539 #define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
6540 #define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
6542 #define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300)
6543 #define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304)
6544 #define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308)
6545 #define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
6546 #define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
6854 #define VLV_CHICKEN_3 (VLV_DISPLAY_BASE + 0x7040C)
7065 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
7066 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
7070 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
7071 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
7075 #define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0)
7093 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
7094 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
7676 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
7677 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
7726 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
7727 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
7734 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)