Lines Matching refs:pipe
477 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, in __i915_enable_pipestat() argument
480 u32 reg = PIPESTAT(pipe); in __i915_enable_pipestat()
489 pipe_name(pipe), enable_mask, status_mask)) in __i915_enable_pipestat()
495 dev_priv->pipestat_irq_mask[pipe] |= status_mask; in __i915_enable_pipestat()
504 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, in __i915_disable_pipestat() argument
507 u32 reg = PIPESTAT(pipe); in __i915_disable_pipestat()
516 pipe_name(pipe), enable_mask, status_mask)) in __i915_disable_pipestat()
522 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; in __i915_disable_pipestat()
558 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, in i915_enable_pipestat() argument
568 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); in i915_enable_pipestat()
572 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, in i915_disable_pipestat() argument
582 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); in i915_disable_pipestat()
656 static u32 i8xx_get_vblank_counter(struct drm_device *dev, unsigned int pipe) in i8xx_get_vblank_counter() argument
665 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe) in i915_get_vblank_counter() argument
672 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); in i915_get_vblank_counter()
687 high_frame = PIPEFRAME(pipe); in i915_get_vblank_counter()
688 low_frame = PIPEFRAMEPIXEL(pipe); in i915_get_vblank_counter()
713 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe) in g4x_get_vblank_counter() argument
717 return I915_READ(PIPE_FRMCOUNT_G4X(pipe)); in g4x_get_vblank_counter()
728 enum pipe pipe = crtc->pipe; in __intel_get_crtc_scanline() local
736 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; in __intel_get_crtc_scanline()
738 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; in __intel_get_crtc_scanline()
757 temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & in __intel_get_crtc_scanline()
773 static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, in i915_get_crtc_scanoutpos() argument
779 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in i915_get_crtc_scanoutpos()
789 "pipe %c\n", pipe_name(pipe)); in i915_get_crtc_scanoutpos()
830 …position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHI… in i915_get_crtc_scanoutpos()
910 static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe, in i915_get_vblank_timestamp() argument
917 if (pipe >= INTEL_INFO(dev)->num_pipes) { in i915_get_vblank_timestamp()
918 DRM_ERROR("Invalid crtc %u\n", pipe); in i915_get_vblank_timestamp()
923 crtc = intel_get_crtc_for_pipe(dev, pipe); in i915_get_vblank_timestamp()
925 DRM_ERROR("Invalid crtc %u\n", pipe); in i915_get_vblank_timestamp()
930 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe); in i915_get_vblank_timestamp()
935 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, in i915_get_vblank_timestamp()
1490 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, in display_pipe_crc_irq_handler() argument
1496 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; in display_pipe_crc_irq_handler()
1519 entry->frame = dev->driver->get_vblank_counter(dev, pipe); in display_pipe_crc_irq_handler()
1535 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, in display_pipe_crc_irq_handler() argument
1542 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) in hsw_pipe_crc_irq_handler() argument
1546 display_pipe_crc_irq_handler(dev, pipe, in hsw_pipe_crc_irq_handler()
1547 I915_READ(PIPE_CRC_RES_1_IVB(pipe)), in hsw_pipe_crc_irq_handler()
1551 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) in ivb_pipe_crc_irq_handler() argument
1555 display_pipe_crc_irq_handler(dev, pipe, in ivb_pipe_crc_irq_handler()
1556 I915_READ(PIPE_CRC_RES_1_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1557 I915_READ(PIPE_CRC_RES_2_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1558 I915_READ(PIPE_CRC_RES_3_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1559 I915_READ(PIPE_CRC_RES_4_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1560 I915_READ(PIPE_CRC_RES_5_IVB(pipe))); in ivb_pipe_crc_irq_handler()
1563 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) in i9xx_pipe_crc_irq_handler() argument
1569 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); in i9xx_pipe_crc_irq_handler()
1574 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); in i9xx_pipe_crc_irq_handler()
1578 display_pipe_crc_irq_handler(dev, pipe, in i9xx_pipe_crc_irq_handler()
1579 I915_READ(PIPE_CRC_RES_RED(pipe)), in i9xx_pipe_crc_irq_handler()
1580 I915_READ(PIPE_CRC_RES_GREEN(pipe)), in i9xx_pipe_crc_irq_handler()
1581 I915_READ(PIPE_CRC_RES_BLUE(pipe)), in i9xx_pipe_crc_irq_handler()
1612 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe) in intel_pipe_handle_vblank() argument
1614 if (!drm_handle_vblank(dev, pipe)) in intel_pipe_handle_vblank()
1624 int pipe; in valleyview_pipestat_irq_handler() local
1627 for_each_pipe(dev_priv, pipe) { in valleyview_pipestat_irq_handler()
1642 switch (pipe) { in valleyview_pipestat_irq_handler()
1654 mask |= dev_priv->pipestat_irq_mask[pipe]; in valleyview_pipestat_irq_handler()
1659 reg = PIPESTAT(pipe); in valleyview_pipestat_irq_handler()
1661 pipe_stats[pipe] = I915_READ(reg) & mask; in valleyview_pipestat_irq_handler()
1666 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | in valleyview_pipestat_irq_handler()
1668 I915_WRITE(reg, pipe_stats[pipe]); in valleyview_pipestat_irq_handler()
1672 for_each_pipe(dev_priv, pipe) { in valleyview_pipestat_irq_handler()
1673 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && in valleyview_pipestat_irq_handler()
1674 intel_pipe_handle_vblank(dev, pipe)) in valleyview_pipestat_irq_handler()
1675 intel_check_page_flip(dev, pipe); in valleyview_pipestat_irq_handler()
1677 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { in valleyview_pipestat_irq_handler()
1678 intel_prepare_page_flip(dev, pipe); in valleyview_pipestat_irq_handler()
1679 intel_finish_page_flip(dev, pipe); in valleyview_pipestat_irq_handler()
1682 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in valleyview_pipestat_irq_handler()
1683 i9xx_pipe_crc_irq_handler(dev, pipe); in valleyview_pipestat_irq_handler()
1685 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in valleyview_pipestat_irq_handler()
1686 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in valleyview_pipestat_irq_handler()
1843 int pipe; in ibx_irq_handler() local
1872 for_each_pipe(dev_priv, pipe) in ibx_irq_handler()
1874 pipe_name(pipe), in ibx_irq_handler()
1875 I915_READ(FDI_RX_IIR(pipe))); in ibx_irq_handler()
1894 enum pipe pipe; in ivb_err_int_handler() local
1899 for_each_pipe(dev_priv, pipe) { in ivb_err_int_handler()
1900 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) in ivb_err_int_handler()
1901 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in ivb_err_int_handler()
1903 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { in ivb_err_int_handler()
1905 ivb_pipe_crc_irq_handler(dev, pipe); in ivb_err_int_handler()
1907 hsw_pipe_crc_irq_handler(dev, pipe); in ivb_err_int_handler()
1937 int pipe; in cpt_irq_handler() local
1963 for_each_pipe(dev_priv, pipe) in cpt_irq_handler()
1965 pipe_name(pipe), in cpt_irq_handler()
1966 I915_READ(FDI_RX_IIR(pipe))); in cpt_irq_handler()
2028 enum pipe pipe; in ilk_display_irq_handler() local
2043 for_each_pipe(dev_priv, pipe) { in ilk_display_irq_handler()
2044 if (de_iir & DE_PIPE_VBLANK(pipe) && in ilk_display_irq_handler()
2045 intel_pipe_handle_vblank(dev, pipe)) in ilk_display_irq_handler()
2046 intel_check_page_flip(dev, pipe); in ilk_display_irq_handler()
2048 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) in ilk_display_irq_handler()
2049 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in ilk_display_irq_handler()
2051 if (de_iir & DE_PIPE_CRC_DONE(pipe)) in ilk_display_irq_handler()
2052 i9xx_pipe_crc_irq_handler(dev, pipe); in ilk_display_irq_handler()
2055 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { in ilk_display_irq_handler()
2056 intel_prepare_page_flip(dev, pipe); in ilk_display_irq_handler()
2057 intel_finish_page_flip_plane(dev, pipe); in ilk_display_irq_handler()
2081 enum pipe pipe; in ivb_display_irq_handler() local
2096 for_each_pipe(dev_priv, pipe) { in ivb_display_irq_handler()
2097 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && in ivb_display_irq_handler()
2098 intel_pipe_handle_vblank(dev, pipe)) in ivb_display_irq_handler()
2099 intel_check_page_flip(dev, pipe); in ivb_display_irq_handler()
2102 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { in ivb_display_irq_handler()
2103 intel_prepare_page_flip(dev, pipe); in ivb_display_irq_handler()
2104 intel_finish_page_flip_plane(dev, pipe); in ivb_display_irq_handler()
2221 enum pipe pipe; in gen8_irq_handler() local
2295 for_each_pipe(dev_priv, pipe) { in gen8_irq_handler()
2298 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) in gen8_irq_handler()
2301 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); in gen8_irq_handler()
2304 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); in gen8_irq_handler()
2307 intel_pipe_handle_vblank(dev, pipe)) in gen8_irq_handler()
2308 intel_check_page_flip(dev, pipe); in gen8_irq_handler()
2316 intel_prepare_page_flip(dev, pipe); in gen8_irq_handler()
2317 intel_finish_page_flip_plane(dev, pipe); in gen8_irq_handler()
2321 hsw_pipe_crc_irq_handler(dev, pipe); in gen8_irq_handler()
2325 pipe); in gen8_irq_handler()
2335 pipe_name(pipe), in gen8_irq_handler()
2489 int pipe, i; in i915_report_and_clear_eir() local
2532 for_each_pipe(dev_priv, pipe) in i915_report_and_clear_eir()
2534 pipe_name(pipe), I915_READ(PIPESTAT(pipe))); in i915_report_and_clear_eir()
2626 static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe) in i915_enable_vblank() argument
2633 i915_enable_pipestat(dev_priv, pipe, in i915_enable_vblank()
2636 i915_enable_pipestat(dev_priv, pipe, in i915_enable_vblank()
2643 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe) in ironlake_enable_vblank() argument
2647 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : in ironlake_enable_vblank()
2648 DE_PIPE_VBLANK(pipe); in ironlake_enable_vblank()
2657 static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe) in valleyview_enable_vblank() argument
2663 i915_enable_pipestat(dev_priv, pipe, in valleyview_enable_vblank()
2670 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe) in gen8_enable_vblank() argument
2676 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; in gen8_enable_vblank()
2677 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in gen8_enable_vblank()
2678 POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); in gen8_enable_vblank()
2686 static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe) in i915_disable_vblank() argument
2692 i915_disable_pipestat(dev_priv, pipe, in i915_disable_vblank()
2698 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe) in ironlake_disable_vblank() argument
2702 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : in ironlake_disable_vblank()
2703 DE_PIPE_VBLANK(pipe); in ironlake_disable_vblank()
2710 static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe) in valleyview_disable_vblank() argument
2716 i915_disable_pipestat(dev_priv, pipe, in valleyview_disable_vblank()
2721 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe) in gen8_disable_vblank() argument
2727 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; in gen8_disable_vblank()
2728 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in gen8_disable_vblank()
2729 POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); in gen8_disable_vblank()
3145 enum pipe pipe; in vlv_display_irq_reset() local
3150 for_each_pipe(dev_priv, pipe) in vlv_display_irq_reset()
3151 I915_WRITE(PIPESTAT(pipe), 0xffff); in vlv_display_irq_reset()
3184 int pipe; in gen8_irq_reset() local
3191 for_each_pipe(dev_priv, pipe) in gen8_irq_reset()
3193 POWER_DOMAIN_PIPE(pipe))) in gen8_irq_reset()
3194 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); in gen8_irq_reset()
3469 enum pipe pipe; in valleyview_display_irqs_install() local
3474 for_each_pipe(dev_priv, pipe) in valleyview_display_irqs_install()
3475 I915_WRITE(PIPESTAT(pipe), pipestat_mask); in valleyview_display_irqs_install()
3482 for_each_pipe(dev_priv, pipe) in valleyview_display_irqs_install()
3483 i915_enable_pipestat(dev_priv, pipe, pipestat_mask); in valleyview_display_irqs_install()
3503 enum pipe pipe; in valleyview_display_irqs_uninstall() local
3522 for_each_pipe(dev_priv, pipe) in valleyview_display_irqs_uninstall()
3523 i915_disable_pipestat(dev_priv, pipe, pipestat_mask); in valleyview_display_irqs_uninstall()
3528 for_each_pipe(dev_priv, pipe) in valleyview_display_irqs_uninstall()
3529 I915_WRITE(PIPESTAT(pipe), pipestat_mask); in valleyview_display_irqs_uninstall()
3634 enum pipe pipe; in gen8_de_irq_postinstall() local
3661 for_each_pipe(dev_priv, pipe) in gen8_de_irq_postinstall()
3663 POWER_DOMAIN_PIPE(pipe))) in gen8_de_irq_postinstall()
3664 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, in gen8_de_irq_postinstall()
3665 dev_priv->de_irq_mask[pipe], in gen8_de_irq_postinstall()
3774 int pipe; in i8xx_irq_preinstall() local
3776 for_each_pipe(dev_priv, pipe) in i8xx_irq_preinstall()
3777 I915_WRITE(PIPESTAT(pipe), 0); in i8xx_irq_preinstall()
3818 int plane, int pipe, u32 iir) in i8xx_handle_vblank() argument
3823 if (!intel_pipe_handle_vblank(dev, pipe)) in i8xx_handle_vblank()
3839 intel_finish_page_flip(dev, pipe); in i8xx_handle_vblank()
3843 intel_check_page_flip(dev, pipe); in i8xx_handle_vblank()
3853 int pipe; in i8xx_irq_handler() local
3875 for_each_pipe(dev_priv, pipe) { in i8xx_irq_handler()
3876 int reg = PIPESTAT(pipe); in i8xx_irq_handler()
3877 pipe_stats[pipe] = I915_READ(reg); in i8xx_irq_handler()
3882 if (pipe_stats[pipe] & 0x8000ffff) in i8xx_irq_handler()
3883 I915_WRITE(reg, pipe_stats[pipe]); in i8xx_irq_handler()
3893 for_each_pipe(dev_priv, pipe) { in i8xx_irq_handler()
3894 int plane = pipe; in i8xx_irq_handler()
3898 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && in i8xx_irq_handler()
3899 i8xx_handle_vblank(dev, plane, pipe, iir)) in i8xx_irq_handler()
3902 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in i8xx_irq_handler()
3903 i9xx_pipe_crc_irq_handler(dev, pipe); in i8xx_irq_handler()
3905 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in i8xx_irq_handler()
3907 pipe); in i8xx_irq_handler()
3919 int pipe; in i8xx_irq_uninstall() local
3921 for_each_pipe(dev_priv, pipe) { in i8xx_irq_uninstall()
3923 I915_WRITE(PIPESTAT(pipe), 0); in i8xx_irq_uninstall()
3924 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); in i8xx_irq_uninstall()
3934 int pipe; in i915_irq_preinstall() local
3942 for_each_pipe(dev_priv, pipe) in i915_irq_preinstall()
3943 I915_WRITE(PIPESTAT(pipe), 0); in i915_irq_preinstall()
4000 int plane, int pipe, u32 iir) in i915_handle_vblank() argument
4005 if (!intel_pipe_handle_vblank(dev, pipe)) in i915_handle_vblank()
4021 intel_finish_page_flip(dev, pipe); in i915_handle_vblank()
4025 intel_check_page_flip(dev, pipe); in i915_handle_vblank()
4037 int pipe, ret = IRQ_NONE; in i915_irq_handler() local
4056 for_each_pipe(dev_priv, pipe) { in i915_irq_handler()
4057 int reg = PIPESTAT(pipe); in i915_irq_handler()
4058 pipe_stats[pipe] = I915_READ(reg); in i915_irq_handler()
4061 if (pipe_stats[pipe] & 0x8000ffff) { in i915_irq_handler()
4062 I915_WRITE(reg, pipe_stats[pipe]); in i915_irq_handler()
4082 for_each_pipe(dev_priv, pipe) { in i915_irq_handler()
4083 int plane = pipe; in i915_irq_handler()
4087 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && in i915_irq_handler()
4088 i915_handle_vblank(dev, plane, pipe, iir)) in i915_irq_handler()
4091 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) in i915_irq_handler()
4094 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in i915_irq_handler()
4095 i9xx_pipe_crc_irq_handler(dev, pipe); in i915_irq_handler()
4097 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in i915_irq_handler()
4099 pipe); in i915_irq_handler()
4130 int pipe; in i915_irq_uninstall() local
4138 for_each_pipe(dev_priv, pipe) { in i915_irq_uninstall()
4140 I915_WRITE(PIPESTAT(pipe), 0); in i915_irq_uninstall()
4141 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); in i915_irq_uninstall()
4152 int pipe; in i965_irq_preinstall() local
4158 for_each_pipe(dev_priv, pipe) in i965_irq_preinstall()
4159 I915_WRITE(PIPESTAT(pipe), 0); in i965_irq_preinstall()
4255 int ret = IRQ_NONE, pipe; in i965_irq_handler() local
4278 for_each_pipe(dev_priv, pipe) { in i965_irq_handler()
4279 int reg = PIPESTAT(pipe); in i965_irq_handler()
4280 pipe_stats[pipe] = I915_READ(reg); in i965_irq_handler()
4285 if (pipe_stats[pipe] & 0x8000ffff) { in i965_irq_handler()
4286 I915_WRITE(reg, pipe_stats[pipe]); in i965_irq_handler()
4309 for_each_pipe(dev_priv, pipe) { in i965_irq_handler()
4310 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && in i965_irq_handler()
4311 i915_handle_vblank(dev, pipe, pipe, iir)) in i965_irq_handler()
4312 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); in i965_irq_handler()
4314 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) in i965_irq_handler()
4317 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in i965_irq_handler()
4318 i9xx_pipe_crc_irq_handler(dev, pipe); in i965_irq_handler()
4320 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in i965_irq_handler()
4321 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in i965_irq_handler()
4354 int pipe; in i965_irq_uninstall() local
4363 for_each_pipe(dev_priv, pipe) in i965_irq_uninstall()
4364 I915_WRITE(PIPESTAT(pipe), 0); in i965_irq_uninstall()
4368 for_each_pipe(dev_priv, pipe) in i965_irq_uninstall()
4369 I915_WRITE(PIPESTAT(pipe), in i965_irq_uninstall()
4370 I915_READ(PIPESTAT(pipe)) & 0x8000ffff); in i965_irq_uninstall()