Lines Matching refs:dev_priv
142 static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, u32 reg) in gen5_assert_iir_is_zero() argument
158 gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
165 gen5_assert_iir_is_zero(dev_priv, type##IIR); \
171 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
175 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv, in i915_hotplug_interrupt_update_locked() argument
181 assert_spin_locked(&dev_priv->irq_lock); in i915_hotplug_interrupt_update_locked()
202 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, in i915_hotplug_interrupt_update() argument
206 spin_lock_irq(&dev_priv->irq_lock); in i915_hotplug_interrupt_update()
207 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits); in i915_hotplug_interrupt_update()
208 spin_unlock_irq(&dev_priv->irq_lock); in i915_hotplug_interrupt_update()
217 static void ilk_update_display_irq(struct drm_i915_private *dev_priv, in ilk_update_display_irq() argument
223 assert_spin_locked(&dev_priv->irq_lock); in ilk_update_display_irq()
227 if (WARN_ON(!intel_irqs_enabled(dev_priv))) in ilk_update_display_irq()
230 new_val = dev_priv->irq_mask; in ilk_update_display_irq()
234 if (new_val != dev_priv->irq_mask) { in ilk_update_display_irq()
235 dev_priv->irq_mask = new_val; in ilk_update_display_irq()
236 I915_WRITE(DEIMR, dev_priv->irq_mask); in ilk_update_display_irq()
242 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) in ironlake_enable_display_irq() argument
244 ilk_update_display_irq(dev_priv, mask, mask); in ironlake_enable_display_irq()
248 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask) in ironlake_disable_display_irq() argument
250 ilk_update_display_irq(dev_priv, mask, 0); in ironlake_disable_display_irq()
259 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, in ilk_update_gt_irq() argument
263 assert_spin_locked(&dev_priv->irq_lock); in ilk_update_gt_irq()
267 if (WARN_ON(!intel_irqs_enabled(dev_priv))) in ilk_update_gt_irq()
270 dev_priv->gt_irq_mask &= ~interrupt_mask; in ilk_update_gt_irq()
271 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); in ilk_update_gt_irq()
272 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); in ilk_update_gt_irq()
276 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) in gen5_enable_gt_irq() argument
278 ilk_update_gt_irq(dev_priv, mask, mask); in gen5_enable_gt_irq()
281 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) in gen5_disable_gt_irq() argument
283 ilk_update_gt_irq(dev_priv, mask, 0); in gen5_disable_gt_irq()
286 static u32 gen6_pm_iir(struct drm_i915_private *dev_priv) in gen6_pm_iir() argument
288 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; in gen6_pm_iir()
291 static u32 gen6_pm_imr(struct drm_i915_private *dev_priv) in gen6_pm_imr() argument
293 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; in gen6_pm_imr()
296 static u32 gen6_pm_ier(struct drm_i915_private *dev_priv) in gen6_pm_ier() argument
298 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; in gen6_pm_ier()
307 static void snb_update_pm_irq(struct drm_i915_private *dev_priv, in snb_update_pm_irq() argument
315 assert_spin_locked(&dev_priv->irq_lock); in snb_update_pm_irq()
317 new_val = dev_priv->pm_irq_mask; in snb_update_pm_irq()
321 if (new_val != dev_priv->pm_irq_mask) { in snb_update_pm_irq()
322 dev_priv->pm_irq_mask = new_val; in snb_update_pm_irq()
323 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask); in snb_update_pm_irq()
324 POSTING_READ(gen6_pm_imr(dev_priv)); in snb_update_pm_irq()
328 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) in gen6_enable_pm_irq() argument
330 if (WARN_ON(!intel_irqs_enabled(dev_priv))) in gen6_enable_pm_irq()
333 snb_update_pm_irq(dev_priv, mask, mask); in gen6_enable_pm_irq()
336 static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv, in __gen6_disable_pm_irq() argument
339 snb_update_pm_irq(dev_priv, mask, 0); in __gen6_disable_pm_irq()
342 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) in gen6_disable_pm_irq() argument
344 if (WARN_ON(!intel_irqs_enabled(dev_priv))) in gen6_disable_pm_irq()
347 __gen6_disable_pm_irq(dev_priv, mask); in gen6_disable_pm_irq()
352 struct drm_i915_private *dev_priv = dev->dev_private; in gen6_reset_rps_interrupts() local
353 uint32_t reg = gen6_pm_iir(dev_priv); in gen6_reset_rps_interrupts()
355 spin_lock_irq(&dev_priv->irq_lock); in gen6_reset_rps_interrupts()
356 I915_WRITE(reg, dev_priv->pm_rps_events); in gen6_reset_rps_interrupts()
357 I915_WRITE(reg, dev_priv->pm_rps_events); in gen6_reset_rps_interrupts()
359 dev_priv->rps.pm_iir = 0; in gen6_reset_rps_interrupts()
360 spin_unlock_irq(&dev_priv->irq_lock); in gen6_reset_rps_interrupts()
365 struct drm_i915_private *dev_priv = dev->dev_private; in gen6_enable_rps_interrupts() local
367 spin_lock_irq(&dev_priv->irq_lock); in gen6_enable_rps_interrupts()
369 WARN_ON(dev_priv->rps.pm_iir); in gen6_enable_rps_interrupts()
370 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); in gen6_enable_rps_interrupts()
371 dev_priv->rps.interrupts_enabled = true; in gen6_enable_rps_interrupts()
372 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) | in gen6_enable_rps_interrupts()
373 dev_priv->pm_rps_events); in gen6_enable_rps_interrupts()
374 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); in gen6_enable_rps_interrupts()
376 spin_unlock_irq(&dev_priv->irq_lock); in gen6_enable_rps_interrupts()
379 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask) in gen6_sanitize_rps_pm_mask() argument
387 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv)) in gen6_sanitize_rps_pm_mask()
390 if (INTEL_INFO(dev_priv)->gen >= 8) in gen6_sanitize_rps_pm_mask()
398 struct drm_i915_private *dev_priv = dev->dev_private; in gen6_disable_rps_interrupts() local
400 spin_lock_irq(&dev_priv->irq_lock); in gen6_disable_rps_interrupts()
401 dev_priv->rps.interrupts_enabled = false; in gen6_disable_rps_interrupts()
402 spin_unlock_irq(&dev_priv->irq_lock); in gen6_disable_rps_interrupts()
404 cancel_work_sync(&dev_priv->rps.work); in gen6_disable_rps_interrupts()
406 spin_lock_irq(&dev_priv->irq_lock); in gen6_disable_rps_interrupts()
408 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0)); in gen6_disable_rps_interrupts()
410 __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events); in gen6_disable_rps_interrupts()
411 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) & in gen6_disable_rps_interrupts()
412 ~dev_priv->pm_rps_events); in gen6_disable_rps_interrupts()
414 spin_unlock_irq(&dev_priv->irq_lock); in gen6_disable_rps_interrupts()
425 static void bdw_update_port_irq(struct drm_i915_private *dev_priv, in bdw_update_port_irq() argument
432 assert_spin_locked(&dev_priv->irq_lock); in bdw_update_port_irq()
436 if (WARN_ON(!intel_irqs_enabled(dev_priv))) in bdw_update_port_irq()
457 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, in ibx_display_interrupt_update() argument
467 assert_spin_locked(&dev_priv->irq_lock); in ibx_display_interrupt_update()
469 if (WARN_ON(!intel_irqs_enabled(dev_priv))) in ibx_display_interrupt_update()
477 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, in __i915_enable_pipestat() argument
483 assert_spin_locked(&dev_priv->irq_lock); in __i915_enable_pipestat()
484 WARN_ON(!intel_irqs_enabled(dev_priv)); in __i915_enable_pipestat()
495 dev_priv->pipestat_irq_mask[pipe] |= status_mask; in __i915_enable_pipestat()
504 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, in __i915_disable_pipestat() argument
510 assert_spin_locked(&dev_priv->irq_lock); in __i915_disable_pipestat()
511 WARN_ON(!intel_irqs_enabled(dev_priv)); in __i915_disable_pipestat()
522 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; in __i915_disable_pipestat()
558 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, in i915_enable_pipestat() argument
563 if (IS_VALLEYVIEW(dev_priv->dev)) in i915_enable_pipestat()
564 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, in i915_enable_pipestat()
568 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); in i915_enable_pipestat()
572 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, in i915_disable_pipestat() argument
577 if (IS_VALLEYVIEW(dev_priv->dev)) in i915_disable_pipestat()
578 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, in i915_disable_pipestat()
582 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); in i915_disable_pipestat()
591 struct drm_i915_private *dev_priv = dev->dev_private; in i915_enable_asle_pipestat() local
593 if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) in i915_enable_asle_pipestat()
596 spin_lock_irq(&dev_priv->irq_lock); in i915_enable_asle_pipestat()
598 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); in i915_enable_asle_pipestat()
600 i915_enable_pipestat(dev_priv, PIPE_A, in i915_enable_asle_pipestat()
603 spin_unlock_irq(&dev_priv->irq_lock); in i915_enable_asle_pipestat()
667 struct drm_i915_private *dev_priv = dev->dev_private; in i915_get_vblank_counter() local
672 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); in i915_get_vblank_counter()
715 struct drm_i915_private *dev_priv = dev->dev_private; in g4x_get_vblank_counter() local
726 struct drm_i915_private *dev_priv = dev->dev_private; in __intel_get_crtc_scanline() local
736 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; in __intel_get_crtc_scanline()
738 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; in __intel_get_crtc_scanline()
757 temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & in __intel_get_crtc_scanline()
778 struct drm_i915_private *dev_priv = dev->dev_private; in i915_get_crtc_scanoutpos() local
779 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in i915_get_crtc_scanoutpos()
812 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in i915_get_crtc_scanoutpos()
830 …position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHI… in i915_get_crtc_scanoutpos()
867 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in i915_get_crtc_scanoutpos()
899 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; in intel_get_crtc_scanline() local
903 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in intel_get_crtc_scanline()
905 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in intel_get_crtc_scanline()
942 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_rps_change_irq_handler() local
950 new_delay = dev_priv->ips.cur_delay; in ironlake_rps_change_irq_handler()
960 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) in ironlake_rps_change_irq_handler()
961 new_delay = dev_priv->ips.cur_delay - 1; in ironlake_rps_change_irq_handler()
962 if (new_delay < dev_priv->ips.max_delay) in ironlake_rps_change_irq_handler()
963 new_delay = dev_priv->ips.max_delay; in ironlake_rps_change_irq_handler()
965 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) in ironlake_rps_change_irq_handler()
966 new_delay = dev_priv->ips.cur_delay + 1; in ironlake_rps_change_irq_handler()
967 if (new_delay > dev_priv->ips.min_delay) in ironlake_rps_change_irq_handler()
968 new_delay = dev_priv->ips.min_delay; in ironlake_rps_change_irq_handler()
972 dev_priv->ips.cur_delay = new_delay; in ironlake_rps_change_irq_handler()
989 static void vlv_c0_read(struct drm_i915_private *dev_priv, in vlv_c0_read() argument
992 ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP); in vlv_c0_read()
997 static bool vlv_c0_above(struct drm_i915_private *dev_priv, in vlv_c0_above() argument
1012 time *= threshold * dev_priv->czclk_freq; in vlv_c0_above()
1025 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv) in gen6_rps_reset_ei() argument
1027 vlv_c0_read(dev_priv, &dev_priv->rps.down_ei); in gen6_rps_reset_ei()
1028 dev_priv->rps.up_ei = dev_priv->rps.down_ei; in gen6_rps_reset_ei()
1031 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) in vlv_wa_c0_ei() argument
1039 vlv_c0_read(dev_priv, &now); in vlv_wa_c0_ei()
1044 if (!vlv_c0_above(dev_priv, in vlv_wa_c0_ei()
1045 &dev_priv->rps.down_ei, &now, in vlv_wa_c0_ei()
1046 dev_priv->rps.down_threshold)) in vlv_wa_c0_ei()
1048 dev_priv->rps.down_ei = now; in vlv_wa_c0_ei()
1052 if (vlv_c0_above(dev_priv, in vlv_wa_c0_ei()
1053 &dev_priv->rps.up_ei, &now, in vlv_wa_c0_ei()
1054 dev_priv->rps.up_threshold)) in vlv_wa_c0_ei()
1056 dev_priv->rps.up_ei = now; in vlv_wa_c0_ei()
1062 static bool any_waiters(struct drm_i915_private *dev_priv) in any_waiters() argument
1067 for_each_ring(ring, dev_priv, i) in any_waiters()
1076 struct drm_i915_private *dev_priv = in gen6_pm_rps_work() local
1082 spin_lock_irq(&dev_priv->irq_lock); in gen6_pm_rps_work()
1084 if (!dev_priv->rps.interrupts_enabled) { in gen6_pm_rps_work()
1085 spin_unlock_irq(&dev_priv->irq_lock); in gen6_pm_rps_work()
1088 pm_iir = dev_priv->rps.pm_iir; in gen6_pm_rps_work()
1089 dev_priv->rps.pm_iir = 0; in gen6_pm_rps_work()
1091 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); in gen6_pm_rps_work()
1092 client_boost = dev_priv->rps.client_boost; in gen6_pm_rps_work()
1093 dev_priv->rps.client_boost = false; in gen6_pm_rps_work()
1094 spin_unlock_irq(&dev_priv->irq_lock); in gen6_pm_rps_work()
1097 WARN_ON(pm_iir & ~dev_priv->pm_rps_events); in gen6_pm_rps_work()
1099 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost) in gen6_pm_rps_work()
1102 mutex_lock(&dev_priv->rps.hw_lock); in gen6_pm_rps_work()
1104 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir); in gen6_pm_rps_work()
1106 adj = dev_priv->rps.last_adj; in gen6_pm_rps_work()
1107 new_delay = dev_priv->rps.cur_freq; in gen6_pm_rps_work()
1108 min = dev_priv->rps.min_freq_softlimit; in gen6_pm_rps_work()
1109 max = dev_priv->rps.max_freq_softlimit; in gen6_pm_rps_work()
1112 new_delay = dev_priv->rps.max_freq_softlimit; in gen6_pm_rps_work()
1118 adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1; in gen6_pm_rps_work()
1123 if (new_delay < dev_priv->rps.efficient_freq - adj) { in gen6_pm_rps_work()
1124 new_delay = dev_priv->rps.efficient_freq; in gen6_pm_rps_work()
1127 } else if (any_waiters(dev_priv)) { in gen6_pm_rps_work()
1130 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) in gen6_pm_rps_work()
1131 new_delay = dev_priv->rps.efficient_freq; in gen6_pm_rps_work()
1133 new_delay = dev_priv->rps.min_freq_softlimit; in gen6_pm_rps_work()
1139 adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1; in gen6_pm_rps_work()
1144 dev_priv->rps.last_adj = adj; in gen6_pm_rps_work()
1152 intel_set_rps(dev_priv->dev, new_delay); in gen6_pm_rps_work()
1154 mutex_unlock(&dev_priv->rps.hw_lock); in gen6_pm_rps_work()
1169 struct drm_i915_private *dev_priv = in ivybridge_parity_work() local
1180 mutex_lock(&dev_priv->dev->struct_mutex); in ivybridge_parity_work()
1183 if (WARN_ON(!dev_priv->l3_parity.which_slice)) in ivybridge_parity_work()
1190 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { in ivybridge_parity_work()
1194 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) in ivybridge_parity_work()
1197 dev_priv->l3_parity.which_slice &= ~(1<<slice); in ivybridge_parity_work()
1216 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, in ivybridge_parity_work()
1231 WARN_ON(dev_priv->l3_parity.which_slice); in ivybridge_parity_work()
1232 spin_lock_irq(&dev_priv->irq_lock); in ivybridge_parity_work()
1233 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); in ivybridge_parity_work()
1234 spin_unlock_irq(&dev_priv->irq_lock); in ivybridge_parity_work()
1236 mutex_unlock(&dev_priv->dev->struct_mutex); in ivybridge_parity_work()
1241 struct drm_i915_private *dev_priv = dev->dev_private; in ivybridge_parity_error_irq_handler() local
1246 spin_lock(&dev_priv->irq_lock); in ivybridge_parity_error_irq_handler()
1247 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); in ivybridge_parity_error_irq_handler()
1248 spin_unlock(&dev_priv->irq_lock); in ivybridge_parity_error_irq_handler()
1252 dev_priv->l3_parity.which_slice |= 1 << 1; in ivybridge_parity_error_irq_handler()
1255 dev_priv->l3_parity.which_slice |= 1 << 0; in ivybridge_parity_error_irq_handler()
1257 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); in ivybridge_parity_error_irq_handler()
1261 struct drm_i915_private *dev_priv, in ilk_gt_irq_handler() argument
1266 notify_ring(&dev_priv->ring[RCS]); in ilk_gt_irq_handler()
1268 notify_ring(&dev_priv->ring[VCS]); in ilk_gt_irq_handler()
1272 struct drm_i915_private *dev_priv, in snb_gt_irq_handler() argument
1278 notify_ring(&dev_priv->ring[RCS]); in snb_gt_irq_handler()
1280 notify_ring(&dev_priv->ring[VCS]); in snb_gt_irq_handler()
1282 notify_ring(&dev_priv->ring[BCS]); in snb_gt_irq_handler()
1293 static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv, in gen8_gt_irq_handler() argument
1305 intel_lrc_irq_handler(&dev_priv->ring[RCS]); in gen8_gt_irq_handler()
1307 notify_ring(&dev_priv->ring[RCS]); in gen8_gt_irq_handler()
1310 intel_lrc_irq_handler(&dev_priv->ring[BCS]); in gen8_gt_irq_handler()
1312 notify_ring(&dev_priv->ring[BCS]); in gen8_gt_irq_handler()
1324 intel_lrc_irq_handler(&dev_priv->ring[VCS]); in gen8_gt_irq_handler()
1326 notify_ring(&dev_priv->ring[VCS]); in gen8_gt_irq_handler()
1329 intel_lrc_irq_handler(&dev_priv->ring[VCS2]); in gen8_gt_irq_handler()
1331 notify_ring(&dev_priv->ring[VCS2]); in gen8_gt_irq_handler()
1343 intel_lrc_irq_handler(&dev_priv->ring[VECS]); in gen8_gt_irq_handler()
1345 notify_ring(&dev_priv->ring[VECS]); in gen8_gt_irq_handler()
1352 if (tmp & dev_priv->pm_rps_events) { in gen8_gt_irq_handler()
1354 tmp & dev_priv->pm_rps_events); in gen8_gt_irq_handler()
1356 gen6_rps_irq_handler(dev_priv, tmp); in gen8_gt_irq_handler()
1477 struct drm_i915_private *dev_priv = dev->dev_private; in gmbus_irq_handler() local
1479 wake_up_all(&dev_priv->gmbus_wait_queue); in gmbus_irq_handler()
1484 struct drm_i915_private *dev_priv = dev->dev_private; in dp_aux_irq_handler() local
1486 wake_up_all(&dev_priv->gmbus_wait_queue); in dp_aux_irq_handler()
1495 struct drm_i915_private *dev_priv = dev->dev_private; in display_pipe_crc_irq_handler() local
1496 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; in display_pipe_crc_irq_handler()
1544 struct drm_i915_private *dev_priv = dev->dev_private; in hsw_pipe_crc_irq_handler() local
1553 struct drm_i915_private *dev_priv = dev->dev_private; in ivb_pipe_crc_irq_handler() local
1565 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_pipe_crc_irq_handler() local
1588 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) in gen6_rps_irq_handler() argument
1590 if (pm_iir & dev_priv->pm_rps_events) { in gen6_rps_irq_handler()
1591 spin_lock(&dev_priv->irq_lock); in gen6_rps_irq_handler()
1592 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); in gen6_rps_irq_handler()
1593 if (dev_priv->rps.interrupts_enabled) { in gen6_rps_irq_handler()
1594 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; in gen6_rps_irq_handler()
1595 queue_work(dev_priv->wq, &dev_priv->rps.work); in gen6_rps_irq_handler()
1597 spin_unlock(&dev_priv->irq_lock); in gen6_rps_irq_handler()
1600 if (INTEL_INFO(dev_priv)->gen >= 8) in gen6_rps_irq_handler()
1603 if (HAS_VEBOX(dev_priv->dev)) { in gen6_rps_irq_handler()
1605 notify_ring(&dev_priv->ring[VECS]); in gen6_rps_irq_handler()
1622 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_pipestat_irq_handler() local
1626 spin_lock(&dev_priv->irq_lock); in valleyview_pipestat_irq_handler()
1627 for_each_pipe(dev_priv, pipe) { in valleyview_pipestat_irq_handler()
1654 mask |= dev_priv->pipestat_irq_mask[pipe]; in valleyview_pipestat_irq_handler()
1670 spin_unlock(&dev_priv->irq_lock); in valleyview_pipestat_irq_handler()
1672 for_each_pipe(dev_priv, pipe) { in valleyview_pipestat_irq_handler()
1686 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in valleyview_pipestat_irq_handler()
1695 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_hpd_irq_handler() local
1737 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_irq_handler() local
1741 if (!intel_irqs_enabled(dev_priv)) in valleyview_irq_handler()
1769 snb_gt_irq_handler(dev, dev_priv, gt_iir); in valleyview_irq_handler()
1771 gen6_rps_irq_handler(dev_priv, pm_iir); in valleyview_irq_handler()
1784 struct drm_i915_private *dev_priv = dev->dev_private; in cherryview_irq_handler() local
1788 if (!intel_irqs_enabled(dev_priv)) in cherryview_irq_handler()
1811 gen8_gt_irq_handler(dev_priv, master_ctl); in cherryview_irq_handler()
1827 struct drm_i915_private *dev_priv = to_i915(dev); in ibx_hpd_irq_handler() local
1842 struct drm_i915_private *dev_priv = dev->dev_private; in ibx_irq_handler() local
1872 for_each_pipe(dev_priv, pipe) in ibx_irq_handler()
1884 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); in ibx_irq_handler()
1887 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); in ibx_irq_handler()
1892 struct drm_i915_private *dev_priv = dev->dev_private; in ivb_err_int_handler() local
1899 for_each_pipe(dev_priv, pipe) { in ivb_err_int_handler()
1901 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in ivb_err_int_handler()
1916 struct drm_i915_private *dev_priv = dev->dev_private; in cpt_serr_int_handler() local
1923 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); in cpt_serr_int_handler()
1926 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); in cpt_serr_int_handler()
1929 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C); in cpt_serr_int_handler()
1936 struct drm_i915_private *dev_priv = dev->dev_private; in cpt_irq_handler() local
1963 for_each_pipe(dev_priv, pipe) in cpt_irq_handler()
1974 struct drm_i915_private *dev_priv = dev->dev_private; in spt_irq_handler() local
2012 struct drm_i915_private *dev_priv = to_i915(dev); in ilk_hpd_irq_handler() local
2027 struct drm_i915_private *dev_priv = dev->dev_private; in ilk_display_irq_handler() local
2043 for_each_pipe(dev_priv, pipe) { in ilk_display_irq_handler()
2049 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in ilk_display_irq_handler()
2080 struct drm_i915_private *dev_priv = dev->dev_private; in ivb_display_irq_handler() local
2096 for_each_pipe(dev_priv, pipe) { in ivb_display_irq_handler()
2130 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_irq_handler() local
2134 if (!intel_irqs_enabled(dev_priv)) in ironlake_irq_handler()
2164 snb_gt_irq_handler(dev, dev_priv, gt_iir); in ironlake_irq_handler()
2166 ilk_gt_irq_handler(dev, dev_priv, gt_iir); in ironlake_irq_handler()
2184 gen6_rps_irq_handler(dev_priv, pm_iir); in ironlake_irq_handler()
2201 struct drm_i915_private *dev_priv = to_i915(dev); in bxt_hpd_irq_handler() local
2217 struct drm_i915_private *dev_priv = dev->dev_private; in gen8_irq_handler() local
2224 if (!intel_irqs_enabled(dev_priv)) in gen8_irq_handler()
2227 if (INTEL_INFO(dev_priv)->gen >= 9) in gen8_irq_handler()
2240 ret = gen8_gt_irq_handler(dev_priv, master_ctl); in gen8_irq_handler()
2262 if (IS_BROXTON(dev_priv)) in gen8_irq_handler()
2264 else if (IS_BROADWELL(dev_priv)) in gen8_irq_handler()
2295 for_each_pipe(dev_priv, pipe) { in gen8_irq_handler()
2310 if (INTEL_INFO(dev_priv)->gen >= 9) in gen8_irq_handler()
2324 intel_cpu_fifo_underrun_irq_handler(dev_priv, in gen8_irq_handler()
2328 if (INTEL_INFO(dev_priv)->gen >= 9) in gen8_irq_handler()
2353 if (HAS_PCH_SPT(dev_priv)) in gen8_irq_handler()
2372 static void i915_error_wake_up(struct drm_i915_private *dev_priv, in i915_error_wake_up() argument
2386 for_each_ring(ring, dev_priv, i) in i915_error_wake_up()
2390 wake_up_all(&dev_priv->pending_flip_queue); in i915_error_wake_up()
2397 wake_up_all(&dev_priv->gpu_error.reset_queue); in i915_error_wake_up()
2409 struct drm_i915_private *dev_priv = to_i915(dev); in i915_reset_and_wakeup() local
2410 struct i915_gpu_error *error = &dev_priv->gpu_error; in i915_reset_and_wakeup()
2440 intel_runtime_pm_get(dev_priv); in i915_reset_and_wakeup()
2454 intel_runtime_pm_put(dev_priv); in i915_reset_and_wakeup()
2468 atomic_inc(&dev_priv->gpu_error.reset_counter); in i915_reset_and_wakeup()
2480 i915_error_wake_up(dev_priv, true); in i915_reset_and_wakeup()
2486 struct drm_i915_private *dev_priv = dev->dev_private; in i915_report_and_clear_eir() local
2532 for_each_pipe(dev_priv, pipe) in i915_report_and_clear_eir()
2589 struct drm_i915_private *dev_priv = dev->dev_private; in i915_handle_error() local
2602 &dev_priv->gpu_error.reset_counter); in i915_handle_error()
2617 i915_error_wake_up(dev_priv, false); in i915_handle_error()
2628 struct drm_i915_private *dev_priv = dev->dev_private; in i915_enable_vblank() local
2631 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in i915_enable_vblank()
2633 i915_enable_pipestat(dev_priv, pipe, in i915_enable_vblank()
2636 i915_enable_pipestat(dev_priv, pipe, in i915_enable_vblank()
2638 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in i915_enable_vblank()
2645 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_enable_vblank() local
2650 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in ironlake_enable_vblank()
2651 ironlake_enable_display_irq(dev_priv, bit); in ironlake_enable_vblank()
2652 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in ironlake_enable_vblank()
2659 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_enable_vblank() local
2662 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in valleyview_enable_vblank()
2663 i915_enable_pipestat(dev_priv, pipe, in valleyview_enable_vblank()
2665 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in valleyview_enable_vblank()
2672 struct drm_i915_private *dev_priv = dev->dev_private; in gen8_enable_vblank() local
2675 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in gen8_enable_vblank()
2676 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; in gen8_enable_vblank()
2677 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in gen8_enable_vblank()
2679 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in gen8_enable_vblank()
2688 struct drm_i915_private *dev_priv = dev->dev_private; in i915_disable_vblank() local
2691 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in i915_disable_vblank()
2692 i915_disable_pipestat(dev_priv, pipe, in i915_disable_vblank()
2695 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in i915_disable_vblank()
2700 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_disable_vblank() local
2705 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in ironlake_disable_vblank()
2706 ironlake_disable_display_irq(dev_priv, bit); in ironlake_disable_vblank()
2707 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in ironlake_disable_vblank()
2712 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_disable_vblank() local
2715 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in valleyview_disable_vblank()
2716 i915_disable_pipestat(dev_priv, pipe, in valleyview_disable_vblank()
2718 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in valleyview_disable_vblank()
2723 struct drm_i915_private *dev_priv = dev->dev_private; in gen8_disable_vblank() local
2726 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in gen8_disable_vblank()
2727 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; in gen8_disable_vblank()
2728 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in gen8_disable_vblank()
2730 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in gen8_disable_vblank()
2755 struct drm_i915_private *dev_priv = ring->dev->dev_private; in semaphore_wait_to_signaller_ring() local
2759 if (INTEL_INFO(dev_priv->dev)->gen >= 8) { in semaphore_wait_to_signaller_ring()
2760 for_each_ring(signaller, dev_priv, i) { in semaphore_wait_to_signaller_ring()
2770 for_each_ring(signaller, dev_priv, i) { in semaphore_wait_to_signaller_ring()
2788 struct drm_i915_private *dev_priv = ring->dev->dev_private; in semaphore_waits_for() local
2858 struct drm_i915_private *dev_priv = ring->dev->dev_private; in semaphore_passed() local
2883 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) in semaphore_clear_deadlocks() argument
2888 for_each_ring(ring, dev_priv, i) in semaphore_clear_deadlocks()
2896 struct drm_i915_private *dev_priv = dev->dev_private; in ring_stuck() local
2953 struct drm_i915_private *dev_priv = in i915_hangcheck_elapsed() local
2954 container_of(work, typeof(*dev_priv), in i915_hangcheck_elapsed()
2956 struct drm_device *dev = dev_priv->dev; in i915_hangcheck_elapsed()
2968 for_each_ring(ring, dev_priv, i) { in i915_hangcheck_elapsed()
2973 semaphore_clear_deadlocks(dev_priv); in i915_hangcheck_elapsed()
2984 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { in i915_hangcheck_elapsed()
2985 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) in i915_hangcheck_elapsed()
3050 for_each_ring(ring, dev_priv, i) { in i915_hangcheck_elapsed()
3086 struct drm_i915_private *dev_priv = dev->dev_private; in ibx_irq_reset() local
3107 struct drm_i915_private *dev_priv = dev->dev_private; in ibx_irq_pre_postinstall() local
3119 struct drm_i915_private *dev_priv = dev->dev_private; in gen5_gt_irq_reset() local
3130 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_irq_reset() local
3143 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) in vlv_display_irq_reset() argument
3147 i915_hotplug_interrupt_update(dev_priv, 0xFFFFFFFF, 0); in vlv_display_irq_reset()
3150 for_each_pipe(dev_priv, pipe) in vlv_display_irq_reset()
3158 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_irq_preinstall() local
3170 vlv_display_irq_reset(dev_priv); in valleyview_irq_preinstall()
3173 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) in gen8_gt_irq_reset() argument
3183 struct drm_i915_private *dev_priv = dev->dev_private; in gen8_irq_reset() local
3189 gen8_gt_irq_reset(dev_priv); in gen8_irq_reset()
3191 for_each_pipe(dev_priv, pipe) in gen8_irq_reset()
3192 if (intel_display_power_is_enabled(dev_priv, in gen8_irq_reset()
3204 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, in gen8_irq_power_well_post_enable() argument
3209 spin_lock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_post_enable()
3212 dev_priv->de_irq_mask[PIPE_A], in gen8_irq_power_well_post_enable()
3213 ~dev_priv->de_irq_mask[PIPE_A] | extra_ier); in gen8_irq_power_well_post_enable()
3216 dev_priv->de_irq_mask[PIPE_B], in gen8_irq_power_well_post_enable()
3217 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); in gen8_irq_power_well_post_enable()
3220 dev_priv->de_irq_mask[PIPE_C], in gen8_irq_power_well_post_enable()
3221 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); in gen8_irq_power_well_post_enable()
3222 spin_unlock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_post_enable()
3227 struct drm_i915_private *dev_priv = dev->dev_private; in cherryview_irq_preinstall() local
3232 gen8_gt_irq_reset(dev_priv); in cherryview_irq_preinstall()
3238 vlv_display_irq_reset(dev_priv); in cherryview_irq_preinstall()
3244 struct drm_i915_private *dev_priv = to_i915(dev); in intel_hpd_enabled_irqs() local
3249 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) in intel_hpd_enabled_irqs()
3257 struct drm_i915_private *dev_priv = dev->dev_private; in ibx_hpd_irq_setup() local
3268 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); in ibx_hpd_irq_setup()
3291 struct drm_i915_private *dev_priv = dev->dev_private; in spt_hpd_irq_setup() local
3297 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); in spt_hpd_irq_setup()
3312 struct drm_i915_private *dev_priv = dev->dev_private; in ilk_hpd_irq_setup() local
3319 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); in ilk_hpd_irq_setup()
3324 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); in ilk_hpd_irq_setup()
3329 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); in ilk_hpd_irq_setup()
3347 struct drm_i915_private *dev_priv = dev->dev_private; in bxt_hpd_irq_setup() local
3353 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); in bxt_hpd_irq_setup()
3363 struct drm_i915_private *dev_priv = dev->dev_private; in ibx_irq_postinstall() local
3374 gen5_assert_iir_is_zero(dev_priv, SDEIIR); in ibx_irq_postinstall()
3380 struct drm_i915_private *dev_priv = dev->dev_private; in gen5_gt_irq_postinstall() local
3385 dev_priv->gt_irq_mask = ~0; in gen5_gt_irq_postinstall()
3388 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); in gen5_gt_irq_postinstall()
3400 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); in gen5_gt_irq_postinstall()
3410 dev_priv->pm_irq_mask = 0xffffffff; in gen5_gt_irq_postinstall()
3411 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); in gen5_gt_irq_postinstall()
3417 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_irq_postinstall() local
3439 dev_priv->irq_mask = ~display_mask; in ironlake_irq_postinstall()
3445 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); in ironlake_irq_postinstall()
3457 spin_lock_irq(&dev_priv->irq_lock); in ironlake_irq_postinstall()
3458 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); in ironlake_irq_postinstall()
3459 spin_unlock_irq(&dev_priv->irq_lock); in ironlake_irq_postinstall()
3465 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv) in valleyview_display_irqs_install() argument
3474 for_each_pipe(dev_priv, pipe) in valleyview_display_irqs_install()
3481 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in valleyview_display_irqs_install()
3482 for_each_pipe(dev_priv, pipe) in valleyview_display_irqs_install()
3483 i915_enable_pipestat(dev_priv, pipe, pipestat_mask); in valleyview_display_irqs_install()
3488 if (IS_CHERRYVIEW(dev_priv)) in valleyview_display_irqs_install()
3490 dev_priv->irq_mask &= ~iir_mask; in valleyview_display_irqs_install()
3494 I915_WRITE(VLV_IER, ~dev_priv->irq_mask); in valleyview_display_irqs_install()
3495 I915_WRITE(VLV_IMR, dev_priv->irq_mask); in valleyview_display_irqs_install()
3499 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv) in valleyview_display_irqs_uninstall() argument
3508 if (IS_CHERRYVIEW(dev_priv)) in valleyview_display_irqs_uninstall()
3511 dev_priv->irq_mask |= iir_mask; in valleyview_display_irqs_uninstall()
3512 I915_WRITE(VLV_IMR, dev_priv->irq_mask); in valleyview_display_irqs_uninstall()
3513 I915_WRITE(VLV_IER, ~dev_priv->irq_mask); in valleyview_display_irqs_uninstall()
3521 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in valleyview_display_irqs_uninstall()
3522 for_each_pipe(dev_priv, pipe) in valleyview_display_irqs_uninstall()
3523 i915_disable_pipestat(dev_priv, pipe, pipestat_mask); in valleyview_display_irqs_uninstall()
3528 for_each_pipe(dev_priv, pipe) in valleyview_display_irqs_uninstall()
3533 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) in valleyview_enable_display_irqs() argument
3535 assert_spin_locked(&dev_priv->irq_lock); in valleyview_enable_display_irqs()
3537 if (dev_priv->display_irqs_enabled) in valleyview_enable_display_irqs()
3540 dev_priv->display_irqs_enabled = true; in valleyview_enable_display_irqs()
3542 if (intel_irqs_enabled(dev_priv)) in valleyview_enable_display_irqs()
3543 valleyview_display_irqs_install(dev_priv); in valleyview_enable_display_irqs()
3546 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) in valleyview_disable_display_irqs() argument
3548 assert_spin_locked(&dev_priv->irq_lock); in valleyview_disable_display_irqs()
3550 if (!dev_priv->display_irqs_enabled) in valleyview_disable_display_irqs()
3553 dev_priv->display_irqs_enabled = false; in valleyview_disable_display_irqs()
3555 if (intel_irqs_enabled(dev_priv)) in valleyview_disable_display_irqs()
3556 valleyview_display_irqs_uninstall(dev_priv); in valleyview_disable_display_irqs()
3559 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) in vlv_display_irq_postinstall() argument
3561 dev_priv->irq_mask = ~0; in vlv_display_irq_postinstall()
3563 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); in vlv_display_irq_postinstall()
3568 I915_WRITE(VLV_IER, ~dev_priv->irq_mask); in vlv_display_irq_postinstall()
3569 I915_WRITE(VLV_IMR, dev_priv->irq_mask); in vlv_display_irq_postinstall()
3574 spin_lock_irq(&dev_priv->irq_lock); in vlv_display_irq_postinstall()
3575 if (dev_priv->display_irqs_enabled) in vlv_display_irq_postinstall()
3576 valleyview_display_irqs_install(dev_priv); in vlv_display_irq_postinstall()
3577 spin_unlock_irq(&dev_priv->irq_lock); in vlv_display_irq_postinstall()
3582 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_irq_postinstall() local
3584 vlv_display_irq_postinstall(dev_priv); in valleyview_irq_postinstall()
3599 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) in gen8_gt_irq_postinstall() argument
3617 dev_priv->pm_irq_mask = 0xffffffff; in gen8_gt_irq_postinstall()
3624 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0); in gen8_gt_irq_postinstall()
3628 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) in gen8_de_irq_postinstall() argument
3636 if (INTEL_INFO(dev_priv)->gen >= 9) { in gen8_de_irq_postinstall()
3641 if (IS_BROXTON(dev_priv)) in gen8_de_irq_postinstall()
3652 if (IS_BROXTON(dev_priv)) in gen8_de_irq_postinstall()
3654 else if (IS_BROADWELL(dev_priv)) in gen8_de_irq_postinstall()
3657 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; in gen8_de_irq_postinstall()
3658 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; in gen8_de_irq_postinstall()
3659 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; in gen8_de_irq_postinstall()
3661 for_each_pipe(dev_priv, pipe) in gen8_de_irq_postinstall()
3662 if (intel_display_power_is_enabled(dev_priv, in gen8_de_irq_postinstall()
3665 dev_priv->de_irq_mask[pipe], in gen8_de_irq_postinstall()
3673 struct drm_i915_private *dev_priv = dev->dev_private; in gen8_irq_postinstall() local
3678 gen8_gt_irq_postinstall(dev_priv); in gen8_irq_postinstall()
3679 gen8_de_irq_postinstall(dev_priv); in gen8_irq_postinstall()
3692 struct drm_i915_private *dev_priv = dev->dev_private; in cherryview_irq_postinstall() local
3694 vlv_display_irq_postinstall(dev_priv); in cherryview_irq_postinstall()
3696 gen8_gt_irq_postinstall(dev_priv); in cherryview_irq_postinstall()
3706 struct drm_i915_private *dev_priv = dev->dev_private; in gen8_irq_uninstall() local
3708 if (!dev_priv) in gen8_irq_uninstall()
3714 static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv) in vlv_display_irq_uninstall() argument
3718 spin_lock_irq(&dev_priv->irq_lock); in vlv_display_irq_uninstall()
3719 if (dev_priv->display_irqs_enabled) in vlv_display_irq_uninstall()
3720 valleyview_display_irqs_uninstall(dev_priv); in vlv_display_irq_uninstall()
3721 spin_unlock_irq(&dev_priv->irq_lock); in vlv_display_irq_uninstall()
3723 vlv_display_irq_reset(dev_priv); in vlv_display_irq_uninstall()
3725 dev_priv->irq_mask = ~0; in vlv_display_irq_uninstall()
3730 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_irq_uninstall() local
3732 if (!dev_priv) in valleyview_irq_uninstall()
3741 vlv_display_irq_uninstall(dev_priv); in valleyview_irq_uninstall()
3746 struct drm_i915_private *dev_priv = dev->dev_private; in cherryview_irq_uninstall() local
3748 if (!dev_priv) in cherryview_irq_uninstall()
3754 gen8_gt_irq_reset(dev_priv); in cherryview_irq_uninstall()
3758 vlv_display_irq_uninstall(dev_priv); in cherryview_irq_uninstall()
3763 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_irq_uninstall() local
3765 if (!dev_priv) in ironlake_irq_uninstall()
3773 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_irq_preinstall() local
3776 for_each_pipe(dev_priv, pipe) in i8xx_irq_preinstall()
3785 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_irq_postinstall() local
3791 dev_priv->irq_mask = in i8xx_irq_postinstall()
3796 I915_WRITE16(IMR, dev_priv->irq_mask); in i8xx_irq_postinstall()
3806 spin_lock_irq(&dev_priv->irq_lock); in i8xx_irq_postinstall()
3807 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
3808 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
3809 spin_unlock_irq(&dev_priv->irq_lock); in i8xx_irq_postinstall()
3820 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_handle_vblank() local
3850 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_irq_handler() local
3858 if (!intel_irqs_enabled(dev_priv)) in i8xx_irq_handler()
3871 spin_lock(&dev_priv->irq_lock); in i8xx_irq_handler()
3875 for_each_pipe(dev_priv, pipe) { in i8xx_irq_handler()
3885 spin_unlock(&dev_priv->irq_lock); in i8xx_irq_handler()
3891 notify_ring(&dev_priv->ring[RCS]); in i8xx_irq_handler()
3893 for_each_pipe(dev_priv, pipe) { in i8xx_irq_handler()
3906 intel_cpu_fifo_underrun_irq_handler(dev_priv, in i8xx_irq_handler()
3918 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_irq_uninstall() local
3921 for_each_pipe(dev_priv, pipe) { in i8xx_irq_uninstall()
3933 struct drm_i915_private *dev_priv = dev->dev_private; in i915_irq_preinstall() local
3937 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); in i915_irq_preinstall()
3942 for_each_pipe(dev_priv, pipe) in i915_irq_preinstall()
3951 struct drm_i915_private *dev_priv = dev->dev_private; in i915_irq_postinstall() local
3957 dev_priv->irq_mask = in i915_irq_postinstall()
3971 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); in i915_irq_postinstall()
3977 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; in i915_irq_postinstall()
3980 I915_WRITE(IMR, dev_priv->irq_mask); in i915_irq_postinstall()
3988 spin_lock_irq(&dev_priv->irq_lock); in i915_irq_postinstall()
3989 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
3990 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
3991 spin_unlock_irq(&dev_priv->irq_lock); in i915_irq_postinstall()
4002 struct drm_i915_private *dev_priv = dev->dev_private; in i915_handle_vblank() local
4032 struct drm_i915_private *dev_priv = dev->dev_private; in i915_irq_handler() local
4039 if (!intel_irqs_enabled(dev_priv)) in i915_irq_handler()
4052 spin_lock(&dev_priv->irq_lock); in i915_irq_handler()
4056 for_each_pipe(dev_priv, pipe) { in i915_irq_handler()
4066 spin_unlock(&dev_priv->irq_lock); in i915_irq_handler()
4080 notify_ring(&dev_priv->ring[RCS]); in i915_irq_handler()
4082 for_each_pipe(dev_priv, pipe) { in i915_irq_handler()
4098 intel_cpu_fifo_underrun_irq_handler(dev_priv, in i915_irq_handler()
4129 struct drm_i915_private *dev_priv = dev->dev_private; in i915_irq_uninstall() local
4133 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); in i915_irq_uninstall()
4138 for_each_pipe(dev_priv, pipe) { in i915_irq_uninstall()
4151 struct drm_i915_private *dev_priv = dev->dev_private; in i965_irq_preinstall() local
4154 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); in i965_irq_preinstall()
4158 for_each_pipe(dev_priv, pipe) in i965_irq_preinstall()
4167 struct drm_i915_private *dev_priv = dev->dev_private; in i965_irq_postinstall() local
4172 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | in i965_irq_postinstall()
4180 enable_mask = ~dev_priv->irq_mask; in i965_irq_postinstall()
4190 spin_lock_irq(&dev_priv->irq_lock); in i965_irq_postinstall()
4191 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in i965_irq_postinstall()
4192 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
4193 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
4194 spin_unlock_irq(&dev_priv->irq_lock); in i965_irq_postinstall()
4211 I915_WRITE(IMR, dev_priv->irq_mask); in i965_irq_postinstall()
4215 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); in i965_irq_postinstall()
4225 struct drm_i915_private *dev_priv = dev->dev_private; in i915_hpd_irq_setup() local
4228 assert_spin_locked(&dev_priv->irq_lock); in i915_hpd_irq_setup()
4242 i915_hotplug_interrupt_update_locked(dev_priv, in i915_hpd_irq_setup()
4252 struct drm_i915_private *dev_priv = dev->dev_private; in i965_irq_handler() local
4260 if (!intel_irqs_enabled(dev_priv)) in i965_irq_handler()
4274 spin_lock(&dev_priv->irq_lock); in i965_irq_handler()
4278 for_each_pipe(dev_priv, pipe) { in i965_irq_handler()
4290 spin_unlock(&dev_priv->irq_lock); in i965_irq_handler()
4305 notify_ring(&dev_priv->ring[RCS]); in i965_irq_handler()
4307 notify_ring(&dev_priv->ring[VCS]); in i965_irq_handler()
4309 for_each_pipe(dev_priv, pipe) { in i965_irq_handler()
4321 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in i965_irq_handler()
4353 struct drm_i915_private *dev_priv = dev->dev_private; in i965_irq_uninstall() local
4356 if (!dev_priv) in i965_irq_uninstall()
4359 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); in i965_irq_uninstall()
4363 for_each_pipe(dev_priv, pipe) in i965_irq_uninstall()
4368 for_each_pipe(dev_priv, pipe) in i965_irq_uninstall()
4381 void intel_irq_init(struct drm_i915_private *dev_priv) in intel_irq_init() argument
4383 struct drm_device *dev = dev_priv->dev; in intel_irq_init()
4385 intel_hpd_init_work(dev_priv); in intel_irq_init()
4387 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); in intel_irq_init()
4388 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); in intel_irq_init()
4391 if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in intel_irq_init()
4393 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED; in intel_irq_init()
4395 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; in intel_irq_init()
4397 INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work, in intel_irq_init()
4400 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); in intel_irq_init()
4402 if (IS_GEN2(dev_priv)) { in intel_irq_init()
4405 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { in intel_irq_init()
4418 if (!IS_GEN2(dev_priv)) in intel_irq_init()
4424 if (IS_CHERRYVIEW(dev_priv)) { in intel_irq_init()
4431 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; in intel_irq_init()
4432 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_irq_init()
4439 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; in intel_irq_init()
4440 } else if (INTEL_INFO(dev_priv)->gen >= 8) { in intel_irq_init()
4448 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; in intel_irq_init()
4450 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup; in intel_irq_init()
4452 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; in intel_irq_init()
4460 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; in intel_irq_init()
4462 if (INTEL_INFO(dev_priv)->gen == 2) { in intel_irq_init()
4467 } else if (INTEL_INFO(dev_priv)->gen == 3) { in intel_irq_init()
4478 if (I915_HAS_HOTPLUG(dev_priv)) in intel_irq_init()
4479 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; in intel_irq_init()
4496 int intel_irq_install(struct drm_i915_private *dev_priv) in intel_irq_install() argument
4503 dev_priv->pm.irqs_enabled = true; in intel_irq_install()
4505 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq); in intel_irq_install()
4515 void intel_irq_uninstall(struct drm_i915_private *dev_priv) in intel_irq_uninstall() argument
4517 drm_irq_uninstall(dev_priv->dev); in intel_irq_uninstall()
4518 intel_hpd_cancel_work(dev_priv); in intel_irq_uninstall()
4519 dev_priv->pm.irqs_enabled = false; in intel_irq_uninstall()
4529 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) in intel_runtime_pm_disable_interrupts() argument
4531 dev_priv->dev->driver->irq_uninstall(dev_priv->dev); in intel_runtime_pm_disable_interrupts()
4532 dev_priv->pm.irqs_enabled = false; in intel_runtime_pm_disable_interrupts()
4533 synchronize_irq(dev_priv->dev->irq); in intel_runtime_pm_disable_interrupts()
4543 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) in intel_runtime_pm_enable_interrupts() argument
4545 dev_priv->pm.irqs_enabled = true; in intel_runtime_pm_enable_interrupts()
4546 dev_priv->dev->driver->irq_preinstall(dev_priv->dev); in intel_runtime_pm_enable_interrupts()
4547 dev_priv->dev->driver->irq_postinstall(dev_priv->dev); in intel_runtime_pm_enable_interrupts()