324 	struct drm_i915_private *dev_priv;  member
406 	void (*mode_set)(struct drm_i915_private *dev_priv,
408 	void (*enable)(struct drm_i915_private *dev_priv,
410 	void (*disable)(struct drm_i915_private *dev_priv,
412 	bool (*get_hw_state)(struct drm_i915_private *dev_priv,
691 	void (*force_wake_get)(struct drm_i915_private *dev_priv,
693 	void (*force_wake_put)(struct drm_i915_private *dev_priv,
696 	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
697 	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
698 	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
699 	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
701 	void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
703 	void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
705 	void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
707 	void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
951 	bool (*fbc_enabled)(struct drm_i915_private *dev_priv);
953 	void (*disable_fbc)(struct drm_i915_private *dev_priv);
1025 	struct drm_i915_private *dev_priv;  member
1205 	void (*sync_hw)(struct drm_i915_private *dev_priv,
1212 	void (*enable)(struct drm_i915_private *dev_priv,
1218 	void (*disable)(struct drm_i915_private *dev_priv,
1221 	bool (*is_enabled)(struct drm_i915_private *dev_priv,
2697 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2698 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2699 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2700 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2701 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2706 void intel_hpd_init(struct drm_i915_private *dev_priv);
2707 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2708 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2717 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2718 int intel_irq_install(struct drm_i915_private *dev_priv);
2719 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2729 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2731 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2736 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2738 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2740 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2747 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2751 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2754 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2755 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2756 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2760 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2762 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2763 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2766 #define ibx_enable_display_interrupt(dev_priv, bits) \  argument
2767 	ibx_display_interrupt_update((dev_priv), (bits), (bits))
2768 #define ibx_disable_display_interrupt(dev_priv, bits) \  argument
2769 	ibx_display_interrupt_update((dev_priv), (bits), 0)
2860 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2965 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)  in i915_stop_ring_allow_ban()  argument
2967 	return dev_priv->gpu_error.stop_rings == 0 ||  in i915_stop_ring_allow_ban()
2968 		dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;  in i915_stop_ring_allow_ban()
2971 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)  in i915_stop_ring_allow_warn()  argument
2973 	return dev_priv->gpu_error.stop_rings == 0 ||  in i915_stop_ring_allow_warn()
2974 		dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;  in i915_stop_ring_allow_warn()
3198 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3201 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3205 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3218 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3225 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3226 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3232 	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;  in i915_gem_object_needs_bit17_swizzle()  local
3234 	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&  in i915_gem_object_needs_bit17_swizzle()
3297 void i915_setup_sysfs(struct drm_device *dev_priv);
3298 void i915_teardown_sysfs(struct drm_device *dev_priv);
3303 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3307 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3365 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3387 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3388 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3391 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3392 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3393 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3394 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3395 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3396 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3397 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3398 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3399 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3400 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3401 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3402 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3403 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3404 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3405 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3406 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3408 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3410 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3411 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3413 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3414 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3416 #define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3417 #define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3419 #define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3420 #define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3421 #define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3422 #define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), f…
3424 #define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3425 #define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3426 #define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3427 #define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), fal…
3435 #define I915_WRITE64(reg, val)	dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3436 #define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3458 #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
3459 #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))