Lines Matching refs:INTEL_INFO
148 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
270 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
273 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
277 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
2444 #define INTEL_INFO(p) (&__I915__(p)->info) macro
2445 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2450 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2452 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2455 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2456 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2457 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2459 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2462 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2463 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2465 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2469 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2470 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2471 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2472 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2473 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2474 #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
2475 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2526 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2527 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2528 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2529 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2530 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2531 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2532 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2533 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2540 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2541 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2542 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2543 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2544 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2547 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2549 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2550 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2555 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2556 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2566 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2567 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2574 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2575 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2577 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2578 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2579 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2584 INTEL_INFO(dev)->gen >= 9)
2586 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2587 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2594 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2595 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2603 INTEL_INFO(dev)->gen >= 8)
2605 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2628 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
3193 if (INTEL_INFO(dev)->gen < 6) in i915_gem_chipset_flush()
3471 else if (INTEL_INFO(dev)->gen >= 5) in i915_vgacntrl_reg()